All Stories

  1. Dynamic light optimization in vertical farming using an IoT-driven digital twin framework and artificial intelligence
  2. Experimental Comparison of TID Hardness in MOSFETs Implemented With the Enclosed, Diamond (Hexagonal Gate), and Rectangular Layout Styles
  3. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  4. Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware
  5. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  6. Differentiated Layout Styles for MOSFETs
  7. Introduction
  8. The MOSFET
  9. Basic Concepts of the Semiconductor Physics
  10. The Electrical Characteristics of the Semiconductor at High Temperatures
  11. The First Generation of the Unconventional Layout Styles for MOSFETs
  12. The Second Generation of the Unconventional Layout Styles (HYBRID) for MOSFETs
  13. The Ionizing Radiations Effects in Electrical Parameters and Figures of Merit of Mosfets
  14. The High Temperatures’ Effects on the Conventional (Rectangular) and Non-conventional Layout Styles of the First and Second Generations for MOSFETs
  15. Using iMTGSPICE to Optimize Cascaded Miller OTAs and Boost Electrical Performance, Robustness and Reduce Die Area
  16. Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs
  17. Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs
  18. Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET
  19. Total Ionizing Dose (X-Ray) Effects on the Mismaching of the Analog MOSFETs layouted with Different Layout Sytles
  20. Impact of using Octogonal Layout Style in Planar Power MOSFETs
  21. New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs
  22. Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE
  23. Comparative Study Between Conventional and Wave Planar Power Mosfets
  24. The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs
  25. LCE and PAMDLE Effects From Diamond Layout for MOSFETs at High-Temperature Ranges
  26. The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures
  27. Optimization of a low noise amplifier with two technology nodes using an interactive evolutionary approach
  28. Boosting the MOSFETs Matching by Using Diamond Layout Style
  29. Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  30. Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs
  31. Zero Temperature Coefficient behavior for Ellipsoidal MOSFET
  32. Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  33. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  34. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  35. A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs
  36. An innovative strategy to reduce die area of robust OTA by using iMTGSPICE and diamond layout style for MOSFETs
  37. Interactive evolutionary approach to reduce the optimization cycle time of a low noise amplifier
  38. Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment
  39. Boosting the Performance of MOSFET Operating Under a Huge Range of High Temperature by Using the Octagonal Layout Style
  40. Boosting the Ionizing Radiation Tolerance in the Mosfets Matching by Using Diamond Layout Style
  41. A Novel Processor Architecture With a Hardware Microkernel to Improve the Performance of Task-Based Systems
  42. Erratum: Impact of designer knowledge in the interactive evolutionary optimisation of analogue CMOS ICs by using iMTGSPICE
  43. Minimizing the TID effects due to gamma rays by using diamond layout for MOSFETs
  44. 8051 Microcontrollers
  45. Impact of designer knowledge in the interactive evolutionary optimization of analog CMOS ICs by using iMTGSPICE
  46. Overview About Radiation–Matter Interaction Mechanisms and Mitigation Techniques
  47. Automatic Optimization of Robust Analog CMOS ICs: An Interactive Genetic Algorithm Driven by Human Knowledge
  48. Using Statistical Student’s t-Test to Qualify the Electrical Performance of the Diamond MOSFETs
  49. Impact of the Octagonal Layout Style for MOSFETs using 180nm Bulk CMOS ICs Technology Node
  50. Improvement Of The Harmonic Distortion By Using Diamond Mosfet
  51. 8051 Core Microcontrollers
  52. Flowchart and Assembly Programming
  53. Fundamental Concepts of Computer Systems
  54. Basic 8051 Core Microcontroller Interruptions
  55. Input/Output Ports of 8051 Core Microcontrollers
  56. Timers/Counters of the 8051 Core Microcontroller
  57. Subroutine and Structuring of the Assembly Programming Language
  58. 8051 Microcontroller Instruction Set of the 8051 Core
  59. The Serial Communication Interface of the 8051 Core Microcontroller
  60. Experimental Study for Mosfet with Ellipsoidal Layout
  61. Using Ellipsoidal Layout Style to Boost the Electrical Performance of the MOSFETs Regarding the 180 nm CMOS ICs Manufacturing Process
  62. Using the Octagonal Layout Style to Implement the Pass MOSFET to Improve the Electrical Performance of the CL–LDO Voltage Regulator
  63. Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits
  64. Improving MOSFETs’ TID Tolerance Through Diamond Layout Style
  65. Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style
  66. VI-Based Measurement System Focusing on Space Applications
  67. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment
  68. Study of proton radiation effects among diamond and rectangular gate MOSFET layouts
  69. Boosting the MOSFETs matching by using diamond layout style
  70. Zero cost layout technique for MOSFETs
  71. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  72. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  73. Layout Techniques for MOSFETS
  74. Introduction
  75. Conclusions and Comments
  76. Ellipsoidal Layout Style for MOSFET
  77. Diamond MOSFET (Hexagonal Gate Geometry)
  78. Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments
  79. Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
  80. From architecture to manufacturing: An accurate framework for optimal OTA design
  81. Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET
  82. Boosting the electrical performance of MOSFET switches by applying Ellipsoidal layout style
  83. An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs
  84. Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment
  85. Diamond layout style impact on SOI MOSFET in high temperature environment
  86. A New Test Environment Approach to SEE Detection in MOSFETs
  87. Non-standard layout styles for MOSFETs
  88. Improving MOSFETs radiation robustness by using the wave layout to boost analog ICs applications
  89. Boosting the radiation hardness and higher reestablishing pre-rad conditions by using OCTO layout style for MOSFETs
  90. Boosting the performance of the planar power MOSFET By using Diamond layout style
  91. HEXAGONAL GATE SHAPE (DIAMOND) FOR MOSFETS
  92. Innovative Layout Styles to Boost the Mosfet Electrical Performance
  93. Experimental comparative study between the diamond MOSFET and its conventional counterpart in high temperatures environment
  94. Analysis of a New Evolutionary System Elitism for Improving the Optimization of a CMOS OTA
  95. Total ionizing dose effects on the digital performance of irradiated OCTO and conventional fully depleted SOI MOSFET
  96. Total ionizing dose radiation effects between the Wave layout style and its conventional counterpart focusing on the digital IC applications
  97. Improving the X-ray radiation tolerance of the analog ICs by using OCTO layout style
  98. OCTO FinFET
  99. Comparative Experimental Study between Tensile and Compressive Uniaxially Stressed nMuGFETs under X-ray Radiation Focusing on Analog Behavior
  100. Projeto de um OTA CMOS por meio de um sistema evolucionário integrado ao SPICE
  101. Using OCTO SOI nMOSFET to Handle High Current for Automotive Modules
  102. Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics
  103. Experimental Comparative Study Between the Wave Layout Style and its Conventional Counterpart for Implementation of Analog Integrated Circuits
  104. Applying the Diamond Layout Style for FinFET
  105. Experimental Study of the OCTO SOI nMOSFET and Its Application in Analog Integrated Circuits
  106. Experimental Validation of the Drain Current Analytical Model of the Fully Depleted Diamond SOI nMOSFETs by Using Paired T-test Statistical Evaluation
  107. Modeling and Characterization of Overlapping Circular-Gate mosfet and Its Application to Power Devices
  108. AGSPICE: A new analog ICs design tool based on evolutionary electronics used for extracting additional design recommendations
  109. Comparative study of the proton beam effects between the conventional and Circular-Gate MOSFETs
  110. Performance of electronic devices submitted to X-rays and high energy proton beams
  111. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  112. X-ray Radiation Effects in Circular-Gate Transistors
  113. FISH SOI MOSFET: Modeling, Characterization and Its Application to Improve the Performance of Analog ICs
  114. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  115. X-ray Radiation Effects in Circular-Gate Transistors
  116. Diamond MOSFET: An innovative layout to improve performance of ICs
  117. Comparative Experimental Study between Diamond and Conventional MOSFET
  118. Comparative Experimental Study between Diamond and Conventional MOSFET
  119. Drain Leakage Current Evaluation in the Diamond SOI nMOSFET at High Temperatures
  120. A Novel Overlapping Circular-Gate Transistor and its Application to Power MOSFETs
  121. The Wave SOI MOSFET: A New Accuracy Transistor Layout to Improve Drain Current and Reduce Die Area for Current Drivers Applications
  122. Using Cynthia SOI MOSFET to Improve Voltage Gain of Analog Integrated Circuits
  123. Early Voltage Behavior in Circular Gate SOI nMOSFET Using 0.13 μm Partially-Depleted SOI CMOS Technology
  124. Comparison Between Harmonic Distortion in Circular Gate and Conventional SOI nMOSFET Using 0.13 [micro sign]m Partially-Depleted SOI CMOS Technology
  125. Implementation of High Performance Operational Transconductance Amplifiers using Graded-Channel SOI nMOSFETs
  126. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
  127. 8051 microcontroller structure
  128. 8051 instruction set
  129. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs