All Stories

  1. Dynamic light optimization in vertical farming using an IoT-driven digital twin framework and artificial intelligence
  2. Experimental Comparison of TID Hardness in MOSFETs Implemented With the Enclosed, Diamond (Hexagonal Gate), and Rectangular Layout Styles
  3. Optimizing RGB Lighting for Lettuce Growth in Vertical Farms with Bio-inspired Optimization Algorithm
  4. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  5. Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware
  6. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  7. Differentiated Layout Styles for MOSFETs
  8. Introduction
  9. The MOSFET
  10. Basic Concepts of the Semiconductor Physics
  11. The Electrical Characteristics of the Semiconductor at High Temperatures
  12. The First Generation of the Unconventional Layout Styles for MOSFETs
  13. The Second Generation of the Unconventional Layout Styles (HYBRID) for MOSFETs
  14. The Ionizing Radiations Effects in Electrical Parameters and Figures of Merit of Mosfets
  15. The High Temperatures’ Effects on the Conventional (Rectangular) and Non-conventional Layout Styles of the First and Second Generations for MOSFETs
  16. Using iMTGSPICE to Optimize Cascaded Miller OTAs and Boost Electrical Performance, Robustness and Reduce Die Area
  17. Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs
  18. Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs
  19. Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET
  20. Total Ionizing Dose (X-Ray) Effects on the Mismaching of the Analog MOSFETs layouted with Different Layout Sytles
  21. Impact of using Octogonal Layout Style in Planar Power MOSFETs
  22. New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs
  23. Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE
  24. Comparative Study Between Conventional and Wave Planar Power Mosfets
  25. The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs
  26. LCE and PAMDLE Effects From Diamond Layout for MOSFETs at High-Temperature Ranges
  27. The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures
  28. Optimization of a low noise amplifier with two technology nodes using an interactive evolutionary approach
  29. Boosting the MOSFETs Matching by Using Diamond Layout Style
  30. Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  31. Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs
  32. Zero Temperature Coefficient behavior for Ellipsoidal MOSFET
  33. Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  34. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  35. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  36. A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs
  37. An innovative strategy to reduce die area of robust OTA by using iMTGSPICE and diamond layout style for MOSFETs
  38. Interactive evolutionary approach to reduce the optimization cycle time of a low noise amplifier
  39. Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment
  40. Boosting the Performance of MOSFET Operating Under a Huge Range of High Temperature by Using the Octagonal Layout Style
  41. Boosting the Ionizing Radiation Tolerance in the Mosfets Matching by Using Diamond Layout Style
  42. A Novel Processor Architecture With a Hardware Microkernel to Improve the Performance of Task-Based Systems
  43. Erratum: Impact of designer knowledge in the interactive evolutionary optimisation of analogue CMOS ICs by using iMTGSPICE
  44. Minimizing the TID effects due to gamma rays by using diamond layout for MOSFETs
  45. 8051 Microcontrollers
  46. Impact of designer knowledge in the interactive evolutionary optimization of analog CMOS ICs by using iMTGSPICE
  47. Overview About Radiation–Matter Interaction Mechanisms and Mitigation Techniques
  48. Automatic Optimization of Robust Analog CMOS ICs: An Interactive Genetic Algorithm Driven by Human Knowledge
  49. Using Statistical Student’s t-Test to Qualify the Electrical Performance of the Diamond MOSFETs
  50. Impact of the Octagonal Layout Style for MOSFETs using 180nm Bulk CMOS ICs Technology Node
  51. Improvement Of The Harmonic Distortion By Using Diamond Mosfet
  52. 8051 Core Microcontrollers
  53. Flowchart and Assembly Programming
  54. Fundamental Concepts of Computer Systems
  55. Basic 8051 Core Microcontroller Interruptions
  56. Input/Output Ports of 8051 Core Microcontrollers
  57. Timers/Counters of the 8051 Core Microcontroller
  58. Subroutine and Structuring of the Assembly Programming Language
  59. 8051 Microcontroller Instruction Set of the 8051 Core
  60. The Serial Communication Interface of the 8051 Core Microcontroller
  61. Experimental Study for Mosfet with Ellipsoidal Layout
  62. Using Ellipsoidal Layout Style to Boost the Electrical Performance of the MOSFETs Regarding the 180 nm CMOS ICs Manufacturing Process
  63. Using the Octagonal Layout Style to Implement the Pass MOSFET to Improve the Electrical Performance of the CL–LDO Voltage Regulator
  64. Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits
  65. Improving MOSFETs’ TID Tolerance Through Diamond Layout Style
  66. Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style
  67. VI-Based Measurement System Focusing on Space Applications
  68. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment
  69. Study of proton radiation effects among diamond and rectangular gate MOSFET layouts
  70. Boosting the MOSFETs matching by using diamond layout style
  71. Zero cost layout technique for MOSFETs
  72. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  73. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  74. Layout Techniques for MOSFETS
  75. Introduction
  76. Conclusions and Comments
  77. Ellipsoidal Layout Style for MOSFET
  78. Diamond MOSFET (Hexagonal Gate Geometry)
  79. Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments
  80. Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
  81. From architecture to manufacturing: An accurate framework for optimal OTA design
  82. Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET
  83. Boosting the electrical performance of MOSFET switches by applying Ellipsoidal layout style
  84. An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs
  85. Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment
  86. Diamond layout style impact on SOI MOSFET in high temperature environment
  87. A New Test Environment Approach to SEE Detection in MOSFETs
  88. Non-standard layout styles for MOSFETs
  89. Improving MOSFETs radiation robustness by using the wave layout to boost analog ICs applications
  90. Boosting the radiation hardness and higher reestablishing pre-rad conditions by using OCTO layout style for MOSFETs
  91. Boosting the performance of the planar power MOSFET By using Diamond layout style
  92. HEXAGONAL GATE SHAPE (DIAMOND) FOR MOSFETS
  93. Innovative Layout Styles to Boost the Mosfet Electrical Performance
  94. Experimental comparative study between the diamond MOSFET and its conventional counterpart in high temperatures environment
  95. Analysis of a New Evolutionary System Elitism for Improving the Optimization of a CMOS OTA
  96. Total ionizing dose effects on the digital performance of irradiated OCTO and conventional fully depleted SOI MOSFET
  97. Total ionizing dose radiation effects between the Wave layout style and its conventional counterpart focusing on the digital IC applications
  98. Improving the X-ray radiation tolerance of the analog ICs by using OCTO layout style
  99. OCTO FinFET
  100. Comparative Experimental Study between Tensile and Compressive Uniaxially Stressed nMuGFETs under X-ray Radiation Focusing on Analog Behavior
  101. Projeto de um OTA CMOS por meio de um sistema evolucionário integrado ao SPICE
  102. Using OCTO SOI nMOSFET to Handle High Current for Automotive Modules
  103. Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics
  104. Experimental Comparative Study Between the Wave Layout Style and its Conventional Counterpart for Implementation of Analog Integrated Circuits
  105. Applying the Diamond Layout Style for FinFET
  106. Experimental Study of the OCTO SOI nMOSFET and Its Application in Analog Integrated Circuits
  107. Experimental Validation of the Drain Current Analytical Model of the Fully Depleted Diamond SOI nMOSFETs by Using Paired T-test Statistical Evaluation
  108. Modeling and Characterization of Overlapping Circular-Gate mosfet and Its Application to Power Devices
  109. AGSPICE: A new analog ICs design tool based on evolutionary electronics used for extracting additional design recommendations
  110. Comparative study of the proton beam effects between the conventional and Circular-Gate MOSFETs
  111. Performance of electronic devices submitted to X-rays and high energy proton beams
  112. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  113. X-ray Radiation Effects in Circular-Gate Transistors
  114. FISH SOI MOSFET: Modeling, Characterization and Its Application to Improve the Performance of Analog ICs
  115. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  116. X-ray Radiation Effects in Circular-Gate Transistors
  117. Diamond MOSFET: An innovative layout to improve performance of ICs
  118. Comparative Experimental Study between Diamond and Conventional MOSFET
  119. Comparative Experimental Study between Diamond and Conventional MOSFET
  120. Drain Leakage Current Evaluation in the Diamond SOI nMOSFET at High Temperatures
  121. A Novel Overlapping Circular-Gate Transistor and its Application to Power MOSFETs
  122. The Wave SOI MOSFET: A New Accuracy Transistor Layout to Improve Drain Current and Reduce Die Area for Current Drivers Applications
  123. Using Cynthia SOI MOSFET to Improve Voltage Gain of Analog Integrated Circuits
  124. Early Voltage Behavior in Circular Gate SOI nMOSFET Using 0.13 μm Partially-Depleted SOI CMOS Technology
  125. Comparison Between Harmonic Distortion in Circular Gate and Conventional SOI nMOSFET Using 0.13 [micro sign]m Partially-Depleted SOI CMOS Technology
  126. Implementation of High Performance Operational Transconductance Amplifiers using Graded-Channel SOI nMOSFETs
  127. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
  128. 8051 microcontroller structure
  129. 8051 instruction set
  130. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs