All Stories

  1. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  2. Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware
  3. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  4. Differentiated Layout Styles for MOSFETs
  5. Introduction
  6. The MOSFET
  7. Basic Concepts of the Semiconductor Physics
  8. The Electrical Characteristics of the Semiconductor at High Temperatures
  9. The First Generation of the Unconventional Layout Styles for MOSFETs
  10. The Second Generation of the Unconventional Layout Styles (HYBRID) for MOSFETs
  11. The Ionizing Radiations Effects in Electrical Parameters and Figures of Merit of Mosfets
  12. The High Temperatures’ Effects on the Conventional (Rectangular) and Non-conventional Layout Styles of the First and Second Generations for MOSFETs
  13. Using iMTGSPICE to Optimize Cascaded Miller OTAs and Boost Electrical Performance, Robustness and Reduce Die Area
  14. Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs
  15. Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET
  16. Total Ionizing Dose (X-Ray) Effects on the Mismaching of the Analog MOSFETs layouted with Different Layout Sytles
  17. New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs
  18. Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE
  19. LCE and PAMDLE Effects From Diamond Layout for MOSFETs at High-Temperature Ranges
  20. The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures
  21. Boosting the MOSFETs Matching by Using Diamond Layout Style
  22. Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  23. Zero Temperature Coefficient behavior for Ellipsoidal MOSFET
  24. Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  25. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  26. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  27. A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs
  28. An innovative strategy to reduce die area of robust OTA by using iMTGSPICE and diamond layout style for MOSFETs
  29. Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment
  30. Boosting the Performance of MOSFET Operating Under a Huge Range of High Temperature by Using the Octagonal Layout Style
  31. Boosting the Ionizing Radiation Tolerance in the Mosfets Matching by Using Diamond Layout Style
  32. A Novel Processor Architecture With a Hardware Microkernel to Improve the Performance of Task-Based Systems
  33. 8051 Microcontrollers
  34. Impact of designer knowledge in the interactive evolutionary optimization of analog CMOS ICs by using iMTGSPICE
  35. Overview About Radiation–Matter Interaction Mechanisms and Mitigation Techniques
  36. Automatic Optimization of Robust Analog CMOS ICs: An Interactive Genetic Algorithm Driven by Human Knowledge
  37. Using Statistical Student’s t-Test to Qualify the Electrical Performance of the Diamond MOSFETs
  38. 8051 Core Microcontrollers
  39. Flowchart and Assembly Programming
  40. Fundamental Concepts of Computer Systems
  41. Basic 8051 Core Microcontroller Interruptions
  42. Input/Output Ports of 8051 Core Microcontrollers
  43. Timers/Counters of the 8051 Core Microcontroller
  44. Subroutine and Structuring of the Assembly Programming Language
  45. 8051 Microcontroller Instruction Set of the 8051 Core
  46. The Serial Communication Interface of the 8051 Core Microcontroller
  47. Experimental Study for Mosfet with Ellipsoidal Layout
  48. Using Ellipsoidal Layout Style to Boost the Electrical Performance of the MOSFETs Regarding the 180 nm CMOS ICs Manufacturing Process
  49. Using the Octagonal Layout Style to Implement the Pass MOSFET to Improve the Electrical Performance of the CL–LDO Voltage Regulator
  50. Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits
  51. Improving MOSFETs’ TID Tolerance Through Diamond Layout Style
  52. Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style
  53. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment
  54. Boosting the MOSFETs matching by using diamond layout style
  55. Zero cost layout technique for MOSFETs
  56. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  57. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  58. Layout Techniques for MOSFETS
  59. Introduction
  60. Conclusions and Comments
  61. Ellipsoidal Layout Style for MOSFET
  62. Diamond MOSFET (Hexagonal Gate Geometry)
  63. Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments
  64. Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
  65. From architecture to manufacturing: An accurate framework for optimal OTA design
  66. Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET
  67. Boosting the electrical performance of MOSFET switches by applying Ellipsoidal layout style
  68. An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs
  69. Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment
  70. Diamond layout style impact on SOI MOSFET in high temperature environment
  71. A New Test Environment Approach to SEE Detection in MOSFETs
  72. Non-standard layout styles for MOSFETs
  73. Improving MOSFETs radiation robustness by using the wave layout to boost analog ICs applications
  74. Boosting the radiation hardness and higher reestablishing pre-rad conditions by using OCTO layout style for MOSFETs
  75. Boosting the performance of the planar power MOSFET By using Diamond layout style
  76. HEXAGONAL GATE SHAPE (DIAMOND) FOR MOSFETS
  77. Innovative Layout Styles to Boost the Mosfet Electrical Performance
  78. Experimental comparative study between the diamond MOSFET and its conventional counterpart in high temperatures environment
  79. Analysis of a New Evolutionary System Elitism for Improving the Optimization of a CMOS OTA
  80. Total ionizing dose effects on the digital performance of irradiated OCTO and conventional fully depleted SOI MOSFET
  81. Total ionizing dose radiation effects between the Wave layout style and its conventional counterpart focusing on the digital IC applications
  82. Improving the X-ray radiation tolerance of the analog ICs by using OCTO layout style
  83. OCTO FinFET
  84. Projeto de um OTA CMOS por meio de um sistema evolucionário integrado ao SPICE
  85. Using OCTO SOI nMOSFET to Handle High Current for Automotive Modules
  86. Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics
  87. Experimental Comparative Study Between the Wave Layout Style and its Conventional Counterpart for Implementation of Analog Integrated Circuits
  88. Modeling and Characterization of Overlapping Circular-Gate mosfet and Its Application to Power Devices
  89. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  90. X-ray Radiation Effects in Circular-Gate Transistors
  91. FISH SOI MOSFET: Modeling, Characterization and Its Application to Improve the Performance of Analog ICs
  92. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  93. X-ray Radiation Effects in Circular-Gate Transistors
  94. Diamond MOSFET: An innovative layout to improve performance of ICs
  95. Comparative Experimental Study between Diamond and Conventional MOSFET
  96. Comparative Experimental Study between Diamond and Conventional MOSFET
  97. Drain Leakage Current Evaluation in the Diamond SOI nMOSFET at High Temperatures
  98. A Novel Overlapping Circular-Gate Transistor and its Application to Power MOSFETs
  99. The Wave SOI MOSFET: A New Accuracy Transistor Layout to Improve Drain Current and Reduce Die Area for Current Drivers Applications
  100. Using Cynthia SOI MOSFET to Improve Voltage Gain of Analog Integrated Circuits
  101. Early Voltage Behavior in Circular Gate SOI nMOSFET Using 0.13 μm Partially-Depleted SOI CMOS Technology
  102. Comparison Between Harmonic Distortion in Circular Gate and Conventional SOI nMOSFET Using 0.13 [micro sign]m Partially-Depleted SOI CMOS Technology
  103. Implementation of High Performance Operational Transconductance Amplifiers using Graded-Channel SOI nMOSFETs
  104. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
  105. 8051 microcontroller structure
  106. 8051 instruction set
  107. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs