All Stories

  1. Boosting the On/Off Current Ratio of MOS Transistor Over a Wide High-Temperature Range Using Second-Generation Layout Style for MOSFETs
  2. Quantitative Validation of Enhanced Matching Stability in Octogonal MOSFETs Under X-ray Radiation: A Multivariate Statistical and Predic-tive Modeling Approach
  3. Geometry-Driven Efficiency Enhancement in PIN–MOS Solar Cells: A Half-Octagonal Design Based on the Longitudinal Corner Effect
  4. An Unsupervised Learning Approach to Validate the Robustness of Octagonal MOSFETs in X-Ray Environments
  5. Experimental Verification and Analytical Modeling of the Zero Temperature Coefficient in Half-Diamond and Diamond MOSFETs Under High-Temperature
  6. AI-Based Design, Optimization, and Validation of a CMOS 65-nm Current Conveyor IC for Chest Electrical Impedance Tomography
  7. A Human–AI Co-Design Methodology for Robust and Compact Miller CMOS OTAs Using the Half-Diamond Layout Style for MOSFETs
  8. Diamond MOSFET as a Statistically Validated Radiation-Hardness-by-Design Solution for High-Dose Gamma Irradiation in 350 nm Bulk CMOS ICs
  9. Enhancing High-Temperature Analog Performance of MOSFETs Through a Half-Diamond Layout Hardness-by-Design Approach
  10. Dynamic light optimization in vertical farming using an IoT-driven digital twin framework and artificial intelligence
  11. Experimental Comparison of TID Hardness in MOSFETs Implemented With the Enclosed, Diamond (Hexagonal Gate), and Rectangular Layout Styles
  12. Optimizing RGB Lighting for Lettuce Growth in Vertical Farms with Bio-inspired Optimization Algorithm
  13. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  14. Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware
  15. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  16. Differentiated Layout Styles for MOSFETs
  17. Introduction
  18. The MOSFET
  19. Basic Concepts of the Semiconductor Physics
  20. The Electrical Characteristics of the Semiconductor at High Temperatures
  21. The First Generation of the Unconventional Layout Styles for MOSFETs
  22. The Second Generation of the Unconventional Layout Styles (HYBRID) for MOSFETs
  23. The Ionizing Radiations Effects in Electrical Parameters and Figures of Merit of Mosfets
  24. The High Temperatures’ Effects on the Conventional (Rectangular) and Non-conventional Layout Styles of the First and Second Generations for MOSFETs
  25. Using iMTGSPICE to Optimize Cascaded Miller OTAs and Boost Electrical Performance, Robustness and Reduce Die Area
  26. Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs
  27. Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs
  28. Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET
  29. Total Ionizing Dose (X-Ray) Effects on the Mismaching of the Analog MOSFETs layouted with Different Layout Sytles
  30. Impact of using Octogonal Layout Style in Planar Power MOSFETs
  31. New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs
  32. Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE
  33. Comparative Study Between Conventional and Wave Planar Power Mosfets
  34. The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs
  35. LCE and PAMDLE Effects From Diamond Layout for MOSFETs at High-Temperature Ranges
  36. The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures
  37. Optimization of a low noise amplifier with two technology nodes using an interactive evolutionary approach
  38. Boosting the MOSFETs Matching by Using Diamond Layout Style
  39. Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  40. Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs
  41. Zero Temperature Coefficient behavior for Ellipsoidal MOSFET
  42. Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  43. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  44. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  45. A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs
  46. An innovative strategy to reduce die area of robust OTA by using iMTGSPICE and diamond layout style for MOSFETs
  47. Interactive evolutionary approach to reduce the optimization cycle time of a low noise amplifier
  48. Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment
  49. Boosting the Performance of MOSFET Operating Under a Huge Range of High Temperature by Using the Octagonal Layout Style
  50. Boosting the Ionizing Radiation Tolerance in the Mosfets Matching by Using Diamond Layout Style
  51. A Novel Processor Architecture With a Hardware Microkernel to Improve the Performance of Task-Based Systems
  52. Erratum: Impact of designer knowledge in the interactive evolutionary optimisation of analogue CMOS ICs by using iMTGSPICE
  53. Minimizing the TID effects due to gamma rays by using diamond layout for MOSFETs
  54. 8051 Microcontrollers
  55. Impact of designer knowledge in the interactive evolutionary optimization of analog CMOS ICs by using iMTGSPICE
  56. Overview About Radiation–Matter Interaction Mechanisms and Mitigation Techniques
  57. Automatic Optimization of Robust Analog CMOS ICs: An Interactive Genetic Algorithm Driven by Human Knowledge
  58. Using Statistical Student’s t-Test to Qualify the Electrical Performance of the Diamond MOSFETs
  59. Impact of the Octagonal Layout Style for MOSFETs using 180nm Bulk CMOS ICs Technology Node
  60. Improvement Of The Harmonic Distortion By Using Diamond Mosfet
  61. 8051 Core Microcontrollers
  62. Flowchart and Assembly Programming
  63. Fundamental Concepts of Computer Systems
  64. Basic 8051 Core Microcontroller Interruptions
  65. Input/Output Ports of 8051 Core Microcontrollers
  66. Timers/Counters of the 8051 Core Microcontroller
  67. Subroutine and Structuring of the Assembly Programming Language
  68. 8051 Microcontroller Instruction Set of the 8051 Core
  69. The Serial Communication Interface of the 8051 Core Microcontroller
  70. Experimental Study for Mosfet with Ellipsoidal Layout
  71. Using Ellipsoidal Layout Style to Boost the Electrical Performance of the MOSFETs Regarding the 180 nm CMOS ICs Manufacturing Process
  72. Using the Octagonal Layout Style to Implement the Pass MOSFET to Improve the Electrical Performance of the CL–LDO Voltage Regulator
  73. Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits
  74. Improving MOSFETs’ TID Tolerance Through Diamond Layout Style
  75. Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style
  76. VI-Based Measurement System Focusing on Space Applications
  77. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment
  78. Study of proton radiation effects among diamond and rectangular gate MOSFET layouts
  79. Boosting the MOSFETs matching by using diamond layout style
  80. Zero cost layout technique for MOSFETs
  81. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  82. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  83. Layout Techniques for MOSFETS
  84. Introduction
  85. Conclusions and Comments
  86. Ellipsoidal Layout Style for MOSFET
  87. Diamond MOSFET (Hexagonal Gate Geometry)
  88. Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments
  89. Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
  90. From architecture to manufacturing: An accurate framework for optimal OTA design
  91. Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET
  92. Boosting the electrical performance of MOSFET switches by applying Ellipsoidal layout style
  93. An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs
  94. Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment
  95. Diamond layout style impact on SOI MOSFET in high temperature environment
  96. A New Test Environment Approach to SEE Detection in MOSFETs
  97. Non-standard layout styles for MOSFETs
  98. Improving MOSFETs radiation robustness by using the wave layout to boost analog ICs applications
  99. Boosting the radiation hardness and higher reestablishing pre-rad conditions by using OCTO layout style for MOSFETs
  100. Boosting the performance of the planar power MOSFET By using Diamond layout style
  101. HEXAGONAL GATE SHAPE (DIAMOND) FOR MOSFETS
  102. Innovative Layout Styles to Boost the Mosfet Electrical Performance
  103. Experimental comparative study between the diamond MOSFET and its conventional counterpart in high temperatures environment
  104. Analysis of a New Evolutionary System Elitism for Improving the Optimization of a CMOS OTA
  105. Total ionizing dose effects on the digital performance of irradiated OCTO and conventional fully depleted SOI MOSFET
  106. Total ionizing dose radiation effects between the Wave layout style and its conventional counterpart focusing on the digital IC applications
  107. Improving the X-ray radiation tolerance of the analog ICs by using OCTO layout style
  108. OCTO FinFET
  109. Comparative Experimental Study between Tensile and Compressive Uniaxially Stressed nMuGFETs under X-ray Radiation Focusing on Analog Behavior
  110. Projeto de um OTA CMOS por meio de um sistema evolucionário integrado ao SPICE
  111. Using OCTO SOI nMOSFET to Handle High Current for Automotive Modules
  112. Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics
  113. Experimental Comparative Study Between the Wave Layout Style and its Conventional Counterpart for Implementation of Analog Integrated Circuits
  114. Applying the Diamond Layout Style for FinFET
  115. Experimental Study of the OCTO SOI nMOSFET and Its Application in Analog Integrated Circuits
  116. Experimental Validation of the Drain Current Analytical Model of the Fully Depleted Diamond SOI nMOSFETs by Using Paired T-test Statistical Evaluation
  117. Modeling and Characterization of Overlapping Circular-Gate mosfet and Its Application to Power Devices
  118. AGSPICE: A new analog ICs design tool based on evolutionary electronics used for extracting additional design recommendations
  119. Comparative study of the proton beam effects between the conventional and Circular-Gate MOSFETs
  120. Performance of electronic devices submitted to X-rays and high energy proton beams
  121. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  122. X-ray Radiation Effects in Circular-Gate Transistors
  123. FISH SOI MOSFET: Modeling, Characterization and Its Application to Improve the Performance of Analog ICs
  124. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  125. X-ray Radiation Effects in Circular-Gate Transistors
  126. Diamond MOSFET: An innovative layout to improve performance of ICs
  127. Comparative Experimental Study between Diamond and Conventional MOSFET
  128. Comparative Experimental Study between Diamond and Conventional MOSFET
  129. Drain Leakage Current Evaluation in the Diamond SOI nMOSFET at High Temperatures
  130. A Novel Overlapping Circular-Gate Transistor and its Application to Power MOSFETs
  131. The Wave SOI MOSFET: A New Accuracy Transistor Layout to Improve Drain Current and Reduce Die Area for Current Drivers Applications
  132. Using Cynthia SOI MOSFET to Improve Voltage Gain of Analog Integrated Circuits
  133. Early Voltage Behavior in Circular Gate SOI nMOSFET Using 0.13 μm Partially-Depleted SOI CMOS Technology
  134. Comparison Between Harmonic Distortion in Circular Gate and Conventional SOI nMOSFET Using 0.13 [micro sign]m Partially-Depleted SOI CMOS Technology
  135. Implementation of High Performance Operational Transconductance Amplifiers using Graded-Channel SOI nMOSFETs
  136. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
  137. 8051 microcontroller structure
  138. 8051 instruction set
  139. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs