All Stories

  1. Geometry-Driven Efficiency Enhancement in PIN–MOS Solar Cells: A Half-Octagonal Design Based on the Longitudinal Corner Effect
  2. An Unsupervised Learning Approach to Validate the Robustness of Octagonal MOSFETs in X-Ray Environments
  3. Experimental Verification and Analytical Modeling of the Zero Temperature Coefficient in Half-Diamond and Diamond MOSFETs Under High-Temperature
  4. Dynamic light optimization in vertical farming using an IoT-driven digital twin framework and artificial intelligence
  5. Experimental Comparison of TID Hardness in MOSFETs Implemented With the Enclosed, Diamond (Hexagonal Gate), and Rectangular Layout Styles
  6. Optimizing RGB Lighting for Lettuce Growth in Vertical Farms with Bio-inspired Optimization Algorithm
  7. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  8. Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware
  9. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  10. Differentiated Layout Styles for MOSFETs
  11. Introduction
  12. The MOSFET
  13. Basic Concepts of the Semiconductor Physics
  14. The Electrical Characteristics of the Semiconductor at High Temperatures
  15. The First Generation of the Unconventional Layout Styles for MOSFETs
  16. The Second Generation of the Unconventional Layout Styles (HYBRID) for MOSFETs
  17. The Ionizing Radiations Effects in Electrical Parameters and Figures of Merit of Mosfets
  18. The High Temperatures’ Effects on the Conventional (Rectangular) and Non-conventional Layout Styles of the First and Second Generations for MOSFETs
  19. Using iMTGSPICE to Optimize Cascaded Miller OTAs and Boost Electrical Performance, Robustness and Reduce Die Area
  20. Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs
  21. Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs
  22. Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET
  23. Total Ionizing Dose (X-Ray) Effects on the Mismaching of the Analog MOSFETs layouted with Different Layout Sytles
  24. Impact of using Octogonal Layout Style in Planar Power MOSFETs
  25. New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs
  26. Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE
  27. Comparative Study Between Conventional and Wave Planar Power Mosfets
  28. The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs
  29. LCE and PAMDLE Effects From Diamond Layout for MOSFETs at High-Temperature Ranges
  30. The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures
  31. Optimization of a low noise amplifier with two technology nodes using an interactive evolutionary approach
  32. Boosting the MOSFETs Matching by Using Diamond Layout Style
  33. Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  34. Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs
  35. Zero Temperature Coefficient behavior for Ellipsoidal MOSFET
  36. Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  37. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  38. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  39. A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs
  40. An innovative strategy to reduce die area of robust OTA by using iMTGSPICE and diamond layout style for MOSFETs
  41. Interactive evolutionary approach to reduce the optimization cycle time of a low noise amplifier
  42. Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment
  43. Boosting the Performance of MOSFET Operating Under a Huge Range of High Temperature by Using the Octagonal Layout Style
  44. Boosting the Ionizing Radiation Tolerance in the Mosfets Matching by Using Diamond Layout Style
  45. A Novel Processor Architecture With a Hardware Microkernel to Improve the Performance of Task-Based Systems
  46. Erratum: Impact of designer knowledge in the interactive evolutionary optimisation of analogue CMOS ICs by using iMTGSPICE
  47. Minimizing the TID effects due to gamma rays by using diamond layout for MOSFETs
  48. 8051 Microcontrollers
  49. Impact of designer knowledge in the interactive evolutionary optimization of analog CMOS ICs by using iMTGSPICE
  50. Overview About Radiation–Matter Interaction Mechanisms and Mitigation Techniques
  51. Automatic Optimization of Robust Analog CMOS ICs: An Interactive Genetic Algorithm Driven by Human Knowledge
  52. Using Statistical Student’s t-Test to Qualify the Electrical Performance of the Diamond MOSFETs
  53. Impact of the Octagonal Layout Style for MOSFETs using 180nm Bulk CMOS ICs Technology Node
  54. Improvement Of The Harmonic Distortion By Using Diamond Mosfet
  55. 8051 Core Microcontrollers
  56. Flowchart and Assembly Programming
  57. Fundamental Concepts of Computer Systems
  58. Basic 8051 Core Microcontroller Interruptions
  59. Input/Output Ports of 8051 Core Microcontrollers
  60. Timers/Counters of the 8051 Core Microcontroller
  61. Subroutine and Structuring of the Assembly Programming Language
  62. 8051 Microcontroller Instruction Set of the 8051 Core
  63. The Serial Communication Interface of the 8051 Core Microcontroller
  64. Experimental Study for Mosfet with Ellipsoidal Layout
  65. Using Ellipsoidal Layout Style to Boost the Electrical Performance of the MOSFETs Regarding the 180 nm CMOS ICs Manufacturing Process
  66. Using the Octagonal Layout Style to Implement the Pass MOSFET to Improve the Electrical Performance of the CL–LDO Voltage Regulator
  67. Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits
  68. Improving MOSFETs’ TID Tolerance Through Diamond Layout Style
  69. Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style
  70. VI-Based Measurement System Focusing on Space Applications
  71. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment
  72. Study of proton radiation effects among diamond and rectangular gate MOSFET layouts
  73. Boosting the MOSFETs matching by using diamond layout style
  74. Zero cost layout technique for MOSFETs
  75. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  76. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  77. Layout Techniques for MOSFETS
  78. Introduction
  79. Conclusions and Comments
  80. Ellipsoidal Layout Style for MOSFET
  81. Diamond MOSFET (Hexagonal Gate Geometry)
  82. Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments
  83. Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
  84. From architecture to manufacturing: An accurate framework for optimal OTA design
  85. Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET
  86. Boosting the electrical performance of MOSFET switches by applying Ellipsoidal layout style
  87. An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs
  88. Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment
  89. Diamond layout style impact on SOI MOSFET in high temperature environment
  90. A New Test Environment Approach to SEE Detection in MOSFETs
  91. Non-standard layout styles for MOSFETs
  92. Improving MOSFETs radiation robustness by using the wave layout to boost analog ICs applications
  93. Boosting the radiation hardness and higher reestablishing pre-rad conditions by using OCTO layout style for MOSFETs
  94. Boosting the performance of the planar power MOSFET By using Diamond layout style
  95. HEXAGONAL GATE SHAPE (DIAMOND) FOR MOSFETS
  96. Innovative Layout Styles to Boost the Mosfet Electrical Performance
  97. Experimental comparative study between the diamond MOSFET and its conventional counterpart in high temperatures environment
  98. Analysis of a New Evolutionary System Elitism for Improving the Optimization of a CMOS OTA
  99. Total ionizing dose effects on the digital performance of irradiated OCTO and conventional fully depleted SOI MOSFET
  100. Total ionizing dose radiation effects between the Wave layout style and its conventional counterpart focusing on the digital IC applications
  101. Improving the X-ray radiation tolerance of the analog ICs by using OCTO layout style
  102. OCTO FinFET
  103. Comparative Experimental Study between Tensile and Compressive Uniaxially Stressed nMuGFETs under X-ray Radiation Focusing on Analog Behavior
  104. Projeto de um OTA CMOS por meio de um sistema evolucionário integrado ao SPICE
  105. Using OCTO SOI nMOSFET to Handle High Current for Automotive Modules
  106. Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics
  107. Experimental Comparative Study Between the Wave Layout Style and its Conventional Counterpart for Implementation of Analog Integrated Circuits
  108. Applying the Diamond Layout Style for FinFET
  109. Experimental Study of the OCTO SOI nMOSFET and Its Application in Analog Integrated Circuits
  110. Experimental Validation of the Drain Current Analytical Model of the Fully Depleted Diamond SOI nMOSFETs by Using Paired T-test Statistical Evaluation
  111. Modeling and Characterization of Overlapping Circular-Gate mosfet and Its Application to Power Devices
  112. AGSPICE: A new analog ICs design tool based on evolutionary electronics used for extracting additional design recommendations
  113. Comparative study of the proton beam effects between the conventional and Circular-Gate MOSFETs
  114. Performance of electronic devices submitted to X-rays and high energy proton beams
  115. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  116. X-ray Radiation Effects in Circular-Gate Transistors
  117. FISH SOI MOSFET: Modeling, Characterization and Its Application to Improve the Performance of Analog ICs
  118. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  119. X-ray Radiation Effects in Circular-Gate Transistors
  120. Diamond MOSFET: An innovative layout to improve performance of ICs
  121. Comparative Experimental Study between Diamond and Conventional MOSFET
  122. Comparative Experimental Study between Diamond and Conventional MOSFET
  123. Drain Leakage Current Evaluation in the Diamond SOI nMOSFET at High Temperatures
  124. A Novel Overlapping Circular-Gate Transistor and its Application to Power MOSFETs
  125. The Wave SOI MOSFET: A New Accuracy Transistor Layout to Improve Drain Current and Reduce Die Area for Current Drivers Applications
  126. Using Cynthia SOI MOSFET to Improve Voltage Gain of Analog Integrated Circuits
  127. Early Voltage Behavior in Circular Gate SOI nMOSFET Using 0.13 μm Partially-Depleted SOI CMOS Technology
  128. Comparison Between Harmonic Distortion in Circular Gate and Conventional SOI nMOSFET Using 0.13 [micro sign]m Partially-Depleted SOI CMOS Technology
  129. Implementation of High Performance Operational Transconductance Amplifiers using Graded-Channel SOI nMOSFETs
  130. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
  131. 8051 microcontroller structure
  132. 8051 instruction set
  133. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs