All Stories

  1. Geometry-Driven Efficiency Enhancement in PIN–MOS Solar Cells: A Half-Octagonal Design Based on the Longitudinal Corner Effect
  2. An Unsupervised Learning Approach to Validate the Robustness of Octagonal MOSFETs in X-Ray Environments
  3. Experimental Verification and Analytical Modeling of the Zero Temperature Coefficient in Half-Diamond and Diamond MOSFETs Under High-Temperature
  4. AI-Based Design, Optimization, and Validation of a CMOS 65-nm Current Conveyor IC for Chest Electrical Impedance Tomography
  5. A Human–AI Co-Design Methodology for Robust and Compact Miller CMOS OTAs Using the Half-Diamond Layout Style for MOSFETs
  6. Dynamic light optimization in vertical farming using an IoT-driven digital twin framework and artificial intelligence
  7. Experimental Comparison of TID Hardness in MOSFETs Implemented With the Enclosed, Diamond (Hexagonal Gate), and Rectangular Layout Styles
  8. Optimizing RGB Lighting for Lettuce Growth in Vertical Farms with Bio-inspired Optimization Algorithm
  9. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  10. Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware
  11. (Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures
  12. Differentiated Layout Styles for MOSFETs
  13. Introduction
  14. The MOSFET
  15. Basic Concepts of the Semiconductor Physics
  16. The Electrical Characteristics of the Semiconductor at High Temperatures
  17. The First Generation of the Unconventional Layout Styles for MOSFETs
  18. The Second Generation of the Unconventional Layout Styles (HYBRID) for MOSFETs
  19. The Ionizing Radiations Effects in Electrical Parameters and Figures of Merit of Mosfets
  20. The High Temperatures’ Effects on the Conventional (Rectangular) and Non-conventional Layout Styles of the First and Second Generations for MOSFETs
  21. Using iMTGSPICE to Optimize Cascaded Miller OTAs and Boost Electrical Performance, Robustness and Reduce Die Area
  22. Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs
  23. Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs
  24. Impact of Temperature Effects in the Zero Temperature Coefficient of the Ellipsoidal MOSFET
  25. Total Ionizing Dose (X-Ray) Effects on the Mismaching of the Analog MOSFETs layouted with Different Layout Sytles
  26. Impact of using Octogonal Layout Style in Planar Power MOSFETs
  27. New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs
  28. Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE
  29. Comparative Study Between Conventional and Wave Planar Power Mosfets
  30. The Second Generation of the Layout Styles for MOSFETs to Further Boosting the Electrical Performance of Analog MOSFETs and CMOS ICs
  31. LCE and PAMDLE Effects From Diamond Layout for MOSFETs at High-Temperature Ranges
  32. The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures
  33. Optimization of a low noise amplifier with two technology nodes using an interactive evolutionary approach
  34. Boosting the MOSFETs Matching by Using Diamond Layout Style
  35. Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  36. Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs
  37. Zero Temperature Coefficient behavior for Ellipsoidal MOSFET
  38. Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments
  39. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  40. Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
  41. A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs
  42. An innovative strategy to reduce die area of robust OTA by using iMTGSPICE and diamond layout style for MOSFETs
  43. Interactive evolutionary approach to reduce the optimization cycle time of a low noise amplifier
  44. Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment
  45. Boosting the Performance of MOSFET Operating Under a Huge Range of High Temperature by Using the Octagonal Layout Style
  46. Boosting the Ionizing Radiation Tolerance in the Mosfets Matching by Using Diamond Layout Style
  47. A Novel Processor Architecture With a Hardware Microkernel to Improve the Performance of Task-Based Systems
  48. Erratum: Impact of designer knowledge in the interactive evolutionary optimisation of analogue CMOS ICs by using iMTGSPICE
  49. Minimizing the TID effects due to gamma rays by using diamond layout for MOSFETs
  50. 8051 Microcontrollers
  51. Impact of designer knowledge in the interactive evolutionary optimization of analog CMOS ICs by using iMTGSPICE
  52. Overview About Radiation–Matter Interaction Mechanisms and Mitigation Techniques
  53. Automatic Optimization of Robust Analog CMOS ICs: An Interactive Genetic Algorithm Driven by Human Knowledge
  54. Using Statistical Student’s t-Test to Qualify the Electrical Performance of the Diamond MOSFETs
  55. Impact of the Octagonal Layout Style for MOSFETs using 180nm Bulk CMOS ICs Technology Node
  56. Improvement Of The Harmonic Distortion By Using Diamond Mosfet
  57. 8051 Core Microcontrollers
  58. Flowchart and Assembly Programming
  59. Fundamental Concepts of Computer Systems
  60. Basic 8051 Core Microcontroller Interruptions
  61. Input/Output Ports of 8051 Core Microcontrollers
  62. Timers/Counters of the 8051 Core Microcontroller
  63. Subroutine and Structuring of the Assembly Programming Language
  64. 8051 Microcontroller Instruction Set of the 8051 Core
  65. The Serial Communication Interface of the 8051 Core Microcontroller
  66. Experimental Study for Mosfet with Ellipsoidal Layout
  67. Using Ellipsoidal Layout Style to Boost the Electrical Performance of the MOSFETs Regarding the 180 nm CMOS ICs Manufacturing Process
  68. Using the Octagonal Layout Style to Implement the Pass MOSFET to Improve the Electrical Performance of the CL–LDO Voltage Regulator
  69. Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits
  70. Improving MOSFETs’ TID Tolerance Through Diamond Layout Style
  71. Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style
  72. VI-Based Measurement System Focusing on Space Applications
  73. Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment
  74. Study of proton radiation effects among diamond and rectangular gate MOSFET layouts
  75. Boosting the MOSFETs matching by using diamond layout style
  76. Zero cost layout technique for MOSFETs
  77. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  78. From architecture to manufacturing: an accurate framework for optimal operational transconductance amplifier design
  79. Layout Techniques for MOSFETS
  80. Introduction
  81. Conclusions and Comments
  82. Ellipsoidal Layout Style for MOSFET
  83. Diamond MOSFET (Hexagonal Gate Geometry)
  84. Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments
  85. Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment
  86. From architecture to manufacturing: An accurate framework for optimal OTA design
  87. Boosting the total ionizing dose tolerance of digital switches by using OCTO SOI MOSFET
  88. Boosting the electrical performance of MOSFET switches by applying Ellipsoidal layout style
  89. An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs
  90. Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment
  91. Diamond layout style impact on SOI MOSFET in high temperature environment
  92. A New Test Environment Approach to SEE Detection in MOSFETs
  93. Non-standard layout styles for MOSFETs
  94. Improving MOSFETs radiation robustness by using the wave layout to boost analog ICs applications
  95. Boosting the radiation hardness and higher reestablishing pre-rad conditions by using OCTO layout style for MOSFETs
  96. Boosting the performance of the planar power MOSFET By using Diamond layout style
  97. HEXAGONAL GATE SHAPE (DIAMOND) FOR MOSFETS
  98. Innovative Layout Styles to Boost the Mosfet Electrical Performance
  99. Experimental comparative study between the diamond MOSFET and its conventional counterpart in high temperatures environment
  100. Analysis of a New Evolutionary System Elitism for Improving the Optimization of a CMOS OTA
  101. Total ionizing dose effects on the digital performance of irradiated OCTO and conventional fully depleted SOI MOSFET
  102. Total ionizing dose radiation effects between the Wave layout style and its conventional counterpart focusing on the digital IC applications
  103. Improving the X-ray radiation tolerance of the analog ICs by using OCTO layout style
  104. OCTO FinFET
  105. Comparative Experimental Study between Tensile and Compressive Uniaxially Stressed nMuGFETs under X-ray Radiation Focusing on Analog Behavior
  106. Projeto de um OTA CMOS por meio de um sistema evolucionário integrado ao SPICE
  107. Using OCTO SOI nMOSFET to Handle High Current for Automotive Modules
  108. Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics
  109. Experimental Comparative Study Between the Wave Layout Style and its Conventional Counterpart for Implementation of Analog Integrated Circuits
  110. Applying the Diamond Layout Style for FinFET
  111. Experimental Study of the OCTO SOI nMOSFET and Its Application in Analog Integrated Circuits
  112. Experimental Validation of the Drain Current Analytical Model of the Fully Depleted Diamond SOI nMOSFETs by Using Paired T-test Statistical Evaluation
  113. Modeling and Characterization of Overlapping Circular-Gate mosfet and Its Application to Power Devices
  114. AGSPICE: A new analog ICs design tool based on evolutionary electronics used for extracting additional design recommendations
  115. Comparative study of the proton beam effects between the conventional and Circular-Gate MOSFETs
  116. Performance of electronic devices submitted to X-rays and high energy proton beams
  117. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  118. X-ray Radiation Effects in Circular-Gate Transistors
  119. FISH SOI MOSFET: Modeling, Characterization and Its Application to Improve the Performance of Analog ICs
  120. FISH SOI MOSFET: An Evolution of the Diamond SOI Transistor for Digital ICs Applications
  121. X-ray Radiation Effects in Circular-Gate Transistors
  122. Diamond MOSFET: An innovative layout to improve performance of ICs
  123. Comparative Experimental Study between Diamond and Conventional MOSFET
  124. Comparative Experimental Study between Diamond and Conventional MOSFET
  125. Drain Leakage Current Evaluation in the Diamond SOI nMOSFET at High Temperatures
  126. A Novel Overlapping Circular-Gate Transistor and its Application to Power MOSFETs
  127. The Wave SOI MOSFET: A New Accuracy Transistor Layout to Improve Drain Current and Reduce Die Area for Current Drivers Applications
  128. Using Cynthia SOI MOSFET to Improve Voltage Gain of Analog Integrated Circuits
  129. Early Voltage Behavior in Circular Gate SOI nMOSFET Using 0.13 μm Partially-Depleted SOI CMOS Technology
  130. Comparison Between Harmonic Distortion in Circular Gate and Conventional SOI nMOSFET Using 0.13 [micro sign]m Partially-Depleted SOI CMOS Technology
  131. Implementation of High Performance Operational Transconductance Amplifiers using Graded-Channel SOI nMOSFETs
  132. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS
  133. 8051 microcontroller structure
  134. 8051 instruction set
  135. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs