All Stories

  1. Static and dynamic compact analytical model for junctionless nanowire transistors

    Article • Journal of Physics Condensed Matter, July 2018, Institute of Physics Publishing

    Prof. Marcelo A Pavanello

  2. Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures

    Article • Semiconductor Science and Technology, August 2017, Institute of Physics Publishing

    Prof. Marcelo A Pavanello

  3. A New Method for Series Resistance Extraction of Nanometer MOSFETs

    Article • IEEE Transactions on Electron Devices, July 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  4. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

    Article • Microelectronic Engineering, June 2017, Elsevier

    Prof. Marcelo A Pavanello

  5. Performance and transport analysis of vertically stacked p-FET SOI nanowires

    Article • April 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  6. Underestimation of measured self-heating in nanowires by using gate resistance technique

    Article • Electronics Letters, November 2016, the Institution of Engineering and Technology (the IET)

    Prof. Marcelo A Pavanello

  7. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

    Article • Semiconductor Science and Technology, October 2016, Institute of Physics Publishing

    Prof. Marcelo A Pavanello

  8. Junctionless nanowire transistors operation at temperatures down to 4.2 K

    Article • Semiconductor Science and Technology, October 2016, Institute of Physics Publishing

    Prof. Marcelo A Pavanello

  9. Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

    Article • Solid-State Electronics, October 2016, Elsevier

    Prof. Marcelo A Pavanello

  10. Influence of the crystal orientation on the operation of junctionless nanowire transistors

    Article • October 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  11. Low power highly linear temperature sensor based on SOI lateral PIN diodes

    Article • October 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  12. Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors

    Article • October 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  13. Analog performance of strained SOI nanowires down to 10K

    Article • September 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  14. Physical insights on the dynamic response of junctionless nanowire transistors

    Article • August 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  15. Non-linearity analysis of triple gate SOI nanowires MOSFETS

    Article • August 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  16. A new series resistance extraction method for junctionless nanowire transistors

    Article • August 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  17. Analysis of carrier mobility in triple gate SOI nFinFET combining rotated substrate and strain

    Article • August 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  18. Charge-based compact analytical model for triple-gate junctionless nanowire transistors

    Article • Solid-State Electronics, August 2016, Elsevier

    Prof. Marcelo A Pavanello

  19. Drain current model for short-channel triple gate junctionless nanowire transistors

    Article • Microelectronics Reliability, August 2016, Elsevier

    Prof. Marcelo A Pavanello

  20. Low-frequency noise in asymmetric self-cascode FD SOI nMOSFETs

    Article • August 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  21. Low-frequency noise of submicron graded-channel SOI nMOSFETs at high temperature

    Article • August 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  22. Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal–oxide–semiconductor field-effect transistors

    Article • IET Circuits Devices & Systems, July 2016, the Institution of Engineering and Technology (the IET)

    Prof. Marcelo A Pavanello

  23. On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

    Article • Solid-State Electronics, March 2016, Elsevier

    Prof. Marcelo A Pavanello

  24. Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors

    Article • IEEE Transactions on Electron Devices, February 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  25. Analog performance of n- and p-FET SOI nanowires including channel length and temperature influence

    Article • January 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  26. Errata to “Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors” [Dec 12 3510-3518]

    Article • IEEE Transactions on Electron Devices, January 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  27. Temperature dependence of the electrical characteristics up to 370 K of amorphous In-Ga-ZnO thin film transistors

    Article • Microelectronics Reliability, January 2016, Elsevier

    Prof. Marcelo A Pavanello

  28. Proposal of compact analytical modeling for trigate junctionless nanowire transistors

    Article • November 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  29. Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

    Article • Microelectronic Engineering, November 2015, Elsevier

    Prof. Marcelo A Pavanello

  30. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs

    Article • Microelectronic Engineering, November 2015, Elsevier

    Prof. Marcelo A Pavanello

  31. Advantages of subthreshold operation of asymmetric self-cascode SOI transistors aiming at analog circuit applications

    Article • October 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  32. Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias

    Article • October 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  33. Quasi-static analytical model for the dynamic operation of triple-gate junctionless nanowire transistors

    Article • October 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  34. Compact model for short-channel symmetric double-gate junctionless transistors

    Article • Solid-State Electronics, September 2015, Elsevier

    Prof. Marcelo A Pavanello

  35. Effective channel length in Junctionless Nanowire Transistors

    Article • August 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  36. Analytical compact model for triple gate junctionless MOSFETs

    Article • August 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  37. Role of the extensions in Double-Gate Junctionless MOSFETs in the drain current at high gate voltage

    Article • August 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  38. Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures

    Article • August 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  39. Asymmetric Self-Cascode versus Graded-Channel SOI nMOSFETs for analog applications

    Article • August 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  40. Detailed analysis of transport properties of FinFETs through Y-Function method: Effects of substrate orientation and strain

    Article • August 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  41. On the origin of low-frequency noise of submicron Graded-Channel fully depleted SOI nMOSFETs

    Article • August 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  42. Simulation Comparison of Self-Heating Effects in Junctionless Nanowire Transistors and FinFET Devices

    Article • ECS Transactions, May 2015, The Electrochemical Society

    Prof. Marcelo A Pavanello

  43. Double-gate junctionless transistor model including short-channel effects

    Article • Semiconductor Science and Technology, April 2015, Institute of Physics Publishing

    Prof. Marcelo A Pavanello

  44. From double to triple gate: Modeling junctionless nanowire transistors

    Article • January 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  45. Improved analog operation of junctionless nanowire transistors using back bias

    Article • January 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  46. Ultra-low-power diodes using junctionless nanowire transistors

    Article • January 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  47. Analog performance of short-channel asymmetric self-cascode of junctionless nanowire nMOS transistors

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  48. Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K

    Article • September 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  49. Improved continuous model for short channel double-gate junctionless transistors

    Article • September 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  50. Effect of high temperature on analog parameters of Asymmetric Self-Cascode SOI nMOSFETs

    Article • September 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  51. Effective mobility analysis of n- and p-types SOI junctionless nanowire transistors

    Article • September 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  52. A simulation study of self-heating effect on junctionless nanowire transistors

    Article • September 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  53. Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias

    Article • September 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  54. Asymmetric self-cascode FD SOI nMOSFETS harmonic distortion at cryogenic temperatures

    Article • July 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  55. Analog operation of Junctionless Nanowire Transistors down to liquid helium temperature

    Article • July 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  56. Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors

    Article • Solid-State Electronics, June 2014, Elsevier

    Prof. Marcelo A Pavanello

  57. Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors

    Article • IEEE Transactions on Electron Devices, May 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  58. Short channel continuous model for double-gate junctionless transistors

    Article • April 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  59. Analysis of harmonic distortion of asymmetric self-cascode association of SOI nMOSFETs operating in saturation

    Article • April 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  60. Compact core model for Symmetric Double-Gate Junctionless Transistors

    Article • Solid-State Electronics, April 2014, Elsevier

    Prof. Marcelo A Pavanello

  61. Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors

    Article • April 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  62. A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors

    Article • Solid-State Electronics, December 2013, Elsevier

    Prof. Marcelo A Pavanello

  63. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates

    Article • Solid-State Electronics, December 2013, Elsevier

    Prof. Marcelo A Pavanello

  64. Analysis of the leakage current in junctionless nanowire transistors

    Article • Applied Physics Letters, November 2013, American Institute of Physics

    Prof. Marcelo A Pavanello

  65. Approximate analytical expression for the tersminal voltage in multi-exponential diode models

    Article • Solid-State Electronics, November 2013, Elsevier

    Prof. Marcelo A Pavanello

  66. Harmonic distortion analysis of short channel junctionless nanowire transistors operating as amplifiers

    Article • October 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  67. Influence of substrate rotation on the low frequency noise of strained triple-gate MuGFETs

    Article • October 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  68. Trap density characterization through low-frequency noise in junctionless transistors

    Article • Microelectronic Engineering, September 2013, Elsevier

    Prof. Marcelo A Pavanello

  69. Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors

    Article • September 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  70. Analytical model for potential in double-gate juntionless transistors

    Article • September 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  71. The influence of the substrate bias in Junctionless nanowire transistors

    Article • September 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  72. Non-linear behavior of Junctionless nanowire transistors operating in the linear regime

    Article • September 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  73. Analysis of charges densities in multiple-gates SOI nMOS junctionless

    Article • September 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  74. Low frequency noise in submicron Graded-Channel SOI MOSFETs

    Article • September 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  75. Physical Characterization of TiOx layers deposited from sol-gel technique

    Article • September 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  76. Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors

    Article • Solid-State Electronics, July 2013, Elsevier

    Prof. Marcelo A Pavanello

  77. Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs

    Article • Microelectronics Reliability, June 2013, Elsevier

    Prof. Marcelo A Pavanello

  78. Analog Behavior of Submicron Graded-Channel SOI MOSFETs Varying Channel Length, Doping Concentration and Temperature

    Article • ECS Transactions, May 2013, The Electrochemical Society

    Prof. Marcelo A Pavanello

  79. Influence of 45  Substrate Rotation on the Analog Performance of Biaxially Strained Silicon SOI MuGFETs

    Article • ECS Transactions, May 2013, The Electrochemical Society

    Prof. Marcelo A Pavanello

  80. Performance of Junctionless Nanowire MOSFET as a Quasi-Linear Resistor

    Article • ECS Transactions, May 2013, The Electrochemical Society

    Prof. Marcelo A Pavanello

  81. Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

    Article • IEEE Transactions on Electron Devices, December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  82. Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs

    Article • October 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  83. Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors

    Article • October 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  84. The role of the incomplete ionization on the operation of Junctionless Nanowire Transistors

    Article • October 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  85. Accounting for Short Channel Effects in the Drain Current Modeling of Junctionless Nanowire Transistors

    Article • ECS Transactions, August 2012, The Electrochemical Society

    Prof. Marcelo A Pavanello

  86. Application of Junctionless Nanowire Transistor in the Self-Cascode Configuration to Improve the Analog Performance

    Article • ECS Transactions, August 2012, The Electrochemical Society

    Prof. Marcelo A Pavanello

  87. Comparative Study of Biaxial and Uniaxial Mechanical Stress Influence on the Low Frequency Noise of Fully Depleted SOI nMOSFETs Operating in Triode and Saturation Regime

    Article • ECS Transactions, August 2012, The Electrochemical Society

    Prof. Marcelo A Pavanello

  88. Intrinsic Gate Capacitances of n-type Junctionless Nanowire Transistors Using a Three-Dimensional Device Simulation and Experimental Measurements

    Article • ECS Transactions, August 2012, The Electrochemical Society

    Prof. Marcelo A Pavanello

  89. Liquid Helium Temperature Operation of Graded-Channel SOI nMOSFETs

    Article • ECS Transactions, August 2012, The Electrochemical Society

    Prof. Marcelo A Pavanello

  90. Simulation of a Miller OpAmp with FinFETs at High Temperatures

    Article • ECS Transactions, August 2012, The Electrochemical Society

    Prof. Marcelo A Pavanello

  91. The zero temperature coefficient in junctionless nanowire transistors

    Article • Applied Physics Letters, August 2012, American Institute of Physics

    Prof. Marcelo A Pavanello

  92. Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs

    Article • Solid-State Electronics, April 2012, Elsevier

    Prof. Marcelo A Pavanello

  93. Simulation of miller OpAmp analog circuit with FinFET transistors

    Article • March 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  94. Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations

    Article • March 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  95. Drain current model for junctionless nanowire transistors

    Article • March 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  96. Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors

    Article • March 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  97. An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices

    Article • Microelectronics Reliability, March 2012, Elsevier

    Prof. Marcelo A Pavanello

  98. Analog performance of submicron GC SOI MOSFETs

    Article • March 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  99. Uniaxial mechanical stress influence on the low frequency noise in FD SOI nMOSFETs operating in saturation

    Article • March 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  100. An explicit multi-exponential model for semiconductor junctions with series and shunt resistances

    Article • Microelectronics Reliability, December 2011, Elsevier

    Prof. Marcelo A Pavanello

  101. Cryogenic Operation of Junctionless Nanowire Transistors

    Article • IEEE Electron Device Letters, October 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  102. Analysis of the Low-Frequency Noise of Junctionless Nanowire Transistors operating in saturation

    Article • October 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  103. Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors

    Article • October 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  104. Threshold voltage in junctionless nanowire transistors

    Article • Semiconductor Science and Technology, September 2011, Institute of Physics Publishing

    Prof. Marcelo A Pavanello

  105. Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

    Article • Solid-State Electronics, August 2011, Elsevier

    Prof. Marcelo A Pavanello

  106. Junctionless Multiple-Gate Transistors for Analog Applications

    Article • IEEE Transactions on Electron Devices, August 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  107. 3D simulation of triple-gate MOSFETs with different mobility regions

    Article • Microelectronic Engineering, July 2011, Elsevier

    Prof. Marcelo A Pavanello

  108. High Temperature Effects on Harmonic Distortion in Submicron SOI Graded-Channel MOSFETs

    Article • Advanced Materials Research, July 2011, Trans Tech Publications

    Prof. Marcelo A Pavanello

  109. Monte Carlo simulation of graded-channel fully depleted SOI nMOSFETs

    Article • February 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  110. Direct determination of threshold condition in DG-MOSFETs from the gm/ID curve

    Article • Solid-State Electronics, February 2011, Elsevier

    Prof. Marcelo A Pavanello

  111. An Analytical Model for the Non-Linearity of Triple Gate SOI MOSFETs

    Article • January 2011, The Electrochemical Society

    Prof. Marcelo A Pavanello

  112. Stress Relaxation Empirical Model for Biaxially Strained Triple-Gate Devices

    Article • January 2011, The Electrochemical Society

    Prof. Marcelo A Pavanello

  113. Performance of Ultra-Low-Power SOI CMOS Diodes Operating at Low Temperatures

    Article • January 2011, The Electrochemical Society

    Prof. Marcelo A Pavanello

  114. Analytical Model for the Threshold Voltage in Junctionless Nanowire Transistors of Different Geometries

    Article • January 2011, The Electrochemical Society

    Prof. Marcelo A Pavanello

  115. Impact of the Series Resistance in the I-V Characteristics of nMOS Junctionless Nanowire Transistors

    Article • January 2011, The Electrochemical Society

    Prof. Marcelo A Pavanello

  116. Comparison between SOI nMOSFET's under Uniaxial and Biaxial Mechanical Stress in Analog Applications

    Article • January 2011, The Electrochemical Society

    Prof. Marcelo A Pavanello

  117. Characterization of Thin-Film SOI PIN Diodes from Cryogenic to Above Room Temperatures Using an Explicit

    Article • January 2011, The Electrochemical Society

    Prof. Marcelo A Pavanello

  118. Impact of Substrate Rotation and Temperature on the Mobility and Series Resistance of Triple-Gate SOI nMOSFETs

    Article • January 2011, The Electrochemical Society

    Prof. Marcelo A Pavanello

  119. The Roles of the Electric Field and the Density of Carriers in the Improved Output Conductance of Junctionless Nanowire Transistors

    Article • January 2011, The Electrochemical Society

    Prof. Marcelo A Pavanello

  120. Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation

    Article • IEEE Transactions on Electron Devices, December 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  121. Analog operation of junctionless transistors at cryogenic temperatures

    Article • October 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  122. Comparison between the behavior of submicron graded-channel SOI nMOSFETs with fully- and partially-depleted operations in a wide temperature range

    Article • October 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  123. Electrical characterization of SOI solar cells in a wide temperature range

    Article • October 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  124. Analysis of Lateral SOI PIN Diodes for the Detection of Blue and UV Wavelengths in a Wide Temperature Range

    Article • January 2010, The Electrochemical Society

    Prof. Marcelo A Pavanello

  125. Analysis of the Low-Frequency Noise in Graded-Channel and Standard SOI nMOSFET

    Article • January 2010, The Electrochemical Society

    Prof. Marcelo A Pavanello

  126. Three-Dimensional Simulation of Biaxially Strained Triple-Gate FinFETs: A Method to Compute the Fin Width and Channel Length Dependences on Device Electrical Characteristics

    Article • January 2010, The Electrochemical Society

    Prof. Marcelo A Pavanello

  127. Simulation of OTA's with Double-Gate Graded-Channel MOSFETS using the Symmetric Doped Double-Gate Model

    Article • January 2010, The Electrochemical Society

    Prof. Marcelo A Pavanello

  128. Analog Operation and Harmonic Distortion Temperature Dependence of nMOS Junctionless Transistors

    Article • January 2010, The Electrochemical Society

    Prof. Marcelo A Pavanello

  129. Parameter Extraction in Quadratic Exponential Junction Model with Series Resistance using Global Lateral Fitting

    Article • January 2010, The Electrochemical Society

    Prof. Marcelo A Pavanello

  130. 3D Simulation of Triple-Gate MOSFETs

    Article • January 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  131. From micro to nano FinFETs: The impact of channel-shape on analog parameters

    Article • December 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  132. Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

    Article • Cryogenics, November 2009, Elsevier

    Prof. Marcelo A Pavanello

  133. Cryogenic operation of FinFETs aiming at analog applications

    Article • Cryogenics, November 2009, Elsevier

    Prof. Marcelo A Pavanello

  134. Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape

    Article • Semiconductor Science and Technology, October 2009, Institute of Physics Publishing

    Prof. Marcelo A Pavanello

  135. Effect of substrate rotation on the analog performance of triple-gate FinFETs

    Article • October 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  136. Thermal sensing performance of lateral SOI PIN diodes in the 90–400 K range

    Article • October 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  137. Analog, RF and nonlinear behaviors of submicron graded channel partially depleted SOI MOSFETs

    Article • September 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  138. Reliability performance characterization of SOI FinFETs

    Article • June 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  139. Analytical Modeling of Double Gate Graded-Channel SOI Transistors for Analog Applications

    Article • January 2009, The Electrochemical Society

    Prof. Marcelo A Pavanello

  140. Harmonic Distortion Analysis of SOI Triple Gate FinFETs Applied to 2-MOS Balanced Structures

    Article • January 2009, The Electrochemical Society

    Prof. Marcelo A Pavanello

  141. Performance of Common-Source, Cascode and Wilson Current Mirrors Implemented with Graded-Channel SOI nMOSFETs in a Wide Temperature Range

    Article • January 2009, The Electrochemical Society

    Prof. Marcelo A Pavanello

  142. On the Performance of Thin-Film Lateral SOI PIN Diodes as Thermal Sensors in a Wide Temperature Range

    Article • January 2009, The Electrochemical Society

    Prof. Marcelo A Pavanello

  143. Influence of Fin Width and Channel Length on the Performance of Buffers Implemented with Standard and Strained Triple-Gate nFinFETs

    Article • January 2009, The Electrochemical Society

    Prof. Marcelo A Pavanello

  144. Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors

    Article • January 2009, The Electrochemical Society

    Prof. Marcelo A Pavanello

  145. Low Temperature and Silicon Thickness Influences on the Threshold Voltage of Double-Gate MOSFETs Considering a Charge Based Extraction Procedure

    Article • January 2009, The Electrochemical Society

    Prof. Marcelo A Pavanello

  146. Fin Width Influence on The Harmonic Distortion of Standard and Strained FinFETs Operating in Saturation

    Article • January 2009, The Electrochemical Society

    Prof. Marcelo A Pavanello

  147. Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer

    Article • Solid-State Electronics, December 2008, Elsevier

    Prof. Marcelo A Pavanello

  148. Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

    Article • Solid-State Electronics, December 2008, Elsevier

    Prof. Marcelo A Pavanello

  149. Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

    Article • Microelectronics Journal, December 2008, Elsevier

    Prof. Marcelo A Pavanello

  150. Strain influence on analog performance of single-gate and FinFET SOI nMOSFETs

    Article • October 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  151. Influence of temperature on the operation of strained triple-gate FinFETs

    Article • October 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  152. 3D Triple-Gate Simulation Considering the Crystallographic Orientations

    Article • January 2008, The Electrochemical Society

    Prof. Marcelo A Pavanello

  153. A Series Association Model For Double Gate Graded-Channel SOI nMOSFET Analog Circuit Simulation

    Article • January 2008, The Electrochemical Society

    Prof. Marcelo A Pavanello

  154. Channel Length Influence on the Performance of Source-Follower Buffers Implemented with Graded-Channel SOI nMOSFETs

    Article • January 2008, The Electrochemical Society

    Prof. Marcelo A Pavanello

  155. Influence of Fin Width on the Intrinsic Voltage Gain of Standard and Strained Triple-Gate nFinFETs

    Article • January 2008, The Electrochemical Society

    Prof. Marcelo A Pavanello

  156. Linearity Analysis in Double Gate Graded-Channel Soi Devices Applied to 2-Mos Mosfet-C Balanced Structures

    Article • January 2008, The Electrochemical Society

    Prof. Marcelo A Pavanello

  157. Analog Operation of Uniaxially Strained FD SOI nMOSFETs in Cryogenic Temperatures

    Article • October 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  158. Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs

    Article • Solid-State Electronics, September 2007, Elsevier

    Prof. Marcelo A Pavanello

  159. Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior

    Article • Microelectronic Engineering, September 2007, Elsevier

    Prof. Marcelo A Pavanello

  160. Evaluation of triple-gate FinFETs with SiO2–HfO2–TiN gate stack under analog operation

    Article • Solid-State Electronics, February 2007, Elsevier

    Prof. Marcelo A Pavanello

  161. The low-frequency noise behaviour of graded-channel SOI nMOSFETs

    Article • Solid-State Electronics, February 2007, Elsevier

    Prof. Marcelo A Pavanello

  162. Analysis of Matching in Graded-Channel SOI MOSFETs

    Article • January 2007, The Electrochemical Society

    Prof. Marcelo A Pavanello

  163. Sidewall Angle Influence on the FinFET Analog Parameters

    Article • January 2007, The Electrochemical Society

    Prof. Marcelo A Pavanello

  164. Temperature Influences on FinFETs with Undoped Body

    Article • January 2007, The Electrochemical Society

    Prof. Marcelo A Pavanello

  165. Application of Double Gate Graded-Channel SOI in MOSFET-C Balanced Structures

    Article • January 2007, The Electrochemical Society

    Prof. Marcelo A Pavanello

  166. Physical Characterization and Reliability Aspects of MuGFETs

    Article • January 2007, The Electrochemical Society

    Prof. Marcelo A Pavanello

  167. Impact of Graded-Channel SOI MOSFET Application on the Performance of Cascode and Wilson Current Mirrors

    Article • January 2007, The Electrochemical Society

    Prof. Marcelo A Pavanello

  168. Low Temperature Operation of Undoped Body Triple-Gate FinFETs from an Analog Perspective

    Article • January 2007, The Electrochemical Society

    Prof. Marcelo A Pavanello

  169. Evaluation of graded-channel SOI MOSFET operation at high temperatures

    Article • Microelectronics Journal, July 2006, Elsevier

    Prof. Marcelo A Pavanello

  170. Impact of Asymmetric Channel Configuration on the Linearity of Double-Gate SOI MOSFETs

    Article • April 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  171. Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications

    Article • Microelectronics Journal, February 2006, Elsevier

    Prof. Marcelo A Pavanello

  172. Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS

    Article • Microelectronics Journal, January 2006, Elsevier

    Dr Salvador Pinillos Gimenez, Prof. Marcelo A Pavanello

  173. High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures

    Article • Solid-State Electronics, October 2005, Elsevier

    Prof. Marcelo A Pavanello

  174. A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation

    Article • Solid-State Electronics, October 2005, Elsevier

    Prof. Marcelo A Pavanello

  175. Analysis of Temperature-Induced Saturation Threshold Voltage Degradation in Deep-Submicrometer Ultrathin SOI MOSFETs

    Article • IEEE Transactions on Electron Devices, October 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  176. Impact of halo implantation on 0.13μm floating body partially depleted SOI n-MOSFETs in low temperature operation

    Article • Solid-State Electronics, August 2005, Elsevier

    Prof. Marcelo A Pavanello

  177. Advantages of the Graded-Channel SOI FD MOSFET for Application as a Quasi-Linear Resistor

    Article • IEEE Transactions on Electron Devices, May 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  178. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs

    Article • Solid-State Electronics, August 2002, Elsevier

    Prof. Marcelo A Pavanello

  179. Analog performance and application of graded-channel fully depleted SOI MOSFETs

    Article • Solid-State Electronics, July 2000, Elsevier

    Prof. Marcelo A Pavanello

  180. Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects

    Article • Solid-State Electronics, June 2000, Elsevier

    Prof. Marcelo A Pavanello

  181. Extraction of the oxide charges at the silicon substrate interface in Silicon-On-Insulator MOSFET's

    Article • Solid-State Electronics, November 1999, Elsevier

    Prof. Marcelo A Pavanello

  182. An Asymmetric Channel SOI nMOSFET for Reducing Parasitic Effects and Improving Output Characteristics

    Article • Electrochemical and Solid-State Letters, January 1999, The Electrochemical Society

    Prof. Marcelo A Pavanello

  183. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature

    Article • Solid-State Electronics, September 1997, Elsevier

    Prof. Marcelo A Pavanello

  184. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77 K

    Article • Microelectronic Engineering, June 1997, Elsevier

    Prof. Marcelo A Pavanello

  185. Substrate influences on fully depleted enhancement mode SOI MOSFETs at room temperature and at 77 K

    Article • Solid-State Electronics, January 1997, Elsevier

    Prof. Marcelo A Pavanello

  186. Graded-Channel SOI nMOSFET Model Valid for Harmonic Distortion Evaluation

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  187. Saturation Threshold Voltage Degradation in Deep-Submicrometer Fully Depleted SOI nMOSFETs Operating in Cryogenic Environments

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  188. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello, Dr Salvador Pinillos Gimenez

  189. A physically-based continuous analytical graded-channel SOI nMOSFET model for analog applications

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello

  190. Analog circuit design using graded-channel SOI nMOSFETs

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Marcelo A Pavanello