Improving MOSFETs’ TID Tolerance Through Diamond Layout Style

  • L. E. Seixas, O. L. Goncalez, R. Souza, S. Finco, R. G. Vaz, G. A. da Silva, S. P. Gimenez
  • IEEE Transactions on Device and Materials Reliability, September 2017, Institute of Electrical & Electronics Engineers (IEEE)
  • DOI: 10.1109/tdmr.2017.2719959

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http://dx.doi.org/10.1109/tdmr.2017.2719959

The following have contributed to this page: Dr Salvador Pinillos Gimenez