Layout Techniques for MOSFETs

  • Salvador Pinillos Gimenez
  • Synthesis Lectures on Emerging Engineering Technologies, March 2016, Morgan & Claypool Publishers LLC
  • DOI: 10.2200/s00704ed1v01y201602eet007

Zero cost layout technique for MOSFETs

What is it about?

Describes how this innovative layout technique was invented in order to boost significantly the electrical performance and ionization radiation tolerance of MOSFETs, without add any extra costs to the CMOS ICs manufacturing processes.

Why is it important?

This layout technique can improve remarkably the electrical performance of the CMOS ICs or to reduce the die area significantly, and simultaneously to improve the ionizing radiation tolerance.

Perspectives

Dr Salvador Pinillos Gimenez
FEI University Center

Innovative layout techniques for MOSFETs still unexplored by the semiconductor and CMOS ICs Industries.

Read Publication

http://dx.doi.org/10.2200/s00704ed1v01y201602eet007

The following have contributed to this page: Dr Salvador Pinillos Gimenez