Compact diamond MOSFET model accounting for PAMDLE applicable down 150 nm node

  • S.P. Gimenez, C. Renaux, E. Davini, V.V. Peruzzi, D. Flandre
  • Electronics Letters, October 2014, the Institution of Engineering and Technology (the IET)
  • DOI: 10.1049/el.2014.1229

Non-standard layout styles for MOSFETs

What is it about?

THIS PAPER DESCRIBES A SIMPLE IDS ANALYTICAL MODEL FOR DIAMOND LAYOUT STYLE (HEXAGONAL GATE SHAPE) FOR MOSFETS, TAKING INTO ACCOUNT THE LCE EFFECT AND NOW THE PAMDLE EFFECT. BESIDES, THIS IDS PROPOSAL ANALYTICAL MODEL IS VALIDATED BY EXPERIMENTAL DATA AND THREE-DIMENSIONAL NUMERICAL SIMULATION UP TO THE ICS CMOS TECHNOLOGY NODE OF 150 NM. LCE AND PAMDLE CONTRIBUTIONS ARE QUANTIFIED BY TWO DIFFERENT ICS CMOS TECHNOLOGIES.

Why is it important?

TODAY THE DESIGNERS CAN PREDICT THE ICS CMOS BEHAVIOR BY USING A SIMPLE IDS DIAMOND ANALYTICAL MODEL TO EXPLORE THE USE OF THIS GATE GEOMETRY TECHNIQUE FOR MOSFET IN ORDER TO BOOST THE ELECTRICAL PERFORMANCE OF THE SEMICONDUCTOR DEVICES AND CONSEQUENTLY OF THE ICS.

Perspectives

Dr Salvador Pinillos Gimenez
FEI University Center

THIS SIMPLE IDS ANALYTICAL MODEL OF THE DIAMOND MOSFET INCORPORATE THE LCE AND PAMDLE EFFECTS AND IT CAN BE USE BY THE CMOS ICS DESIGNERS TO PREDICT THE DEVICES ELECTRICAL PERFOMANCE. BESIDES, IT CAN BE EASILY IMPLEMENTED IN SEMICONDUCTOR DEVICES SIMULATORS TOO.

Read Publication

http://dx.doi.org/10.1049/el.2014.1229

The following have contributed to this page: Dr Salvador Pinillos Gimenez

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