What is it about?

In this paper, a new approach for aging aware CMOS 6T-SRAM design has been proposed. It is based on transistor sizing technique by resizing the cell transistors to enhance cell stability and hence increase its reliability lifetime. The cell stability is analyzed in terms of hold and read static noise margins, and writes ability.

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Why is it important?

The obtained simulation results show that unlike what is widely believed in the literature, transistor sizing can be a powerful tool for overcoming NBTI aging problem in CMOS-SRAMs. The degradation could be shrunk to the half if the cell transistors’ size is doubled.


The accessed transistors are sized for a better hold static noise margin under NBTI, and the others can be sized for improving read stability and write-ability with minimum area overhead.

Pr Hamid Bentarzi
Universite M'Hamed Bougara Boumerdes

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This page is a summary of: On the Sizing of the CMOS 6T-SRAM Cell for NBTI Aging Mitigation, IET Circuits Devices & Systems, February 2020, the Institution of Engineering and Technology (the IET), DOI: 10.1049/iet-cds.2019.0307.
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