All Stories

  1. Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

    Article • International Journal of RF and Microwave Computer-Aided Engineering, August 2021, Wiley

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  2. Capacitance–Voltage Technique Based on Time Varying Magnetic Field for VDMOSFET—Part I: Concept and Implementation

    Article • IEEE Transactions on Electron Devices, May 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  3. Capacitance–Voltage Technique Based on Time Varying Magnetic Field for VDMOSFET—Part II: Measurements and Parameter Extractions

    Article • IEEE Transactions on Electron Devices, May 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  4. Fast Ids – Vgs Technique Implementation for NBTI Characterization

    Article • September 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  5. NBTI lifetime devices

    Article • Microelectronics Reliability, July 2020, Elsevier

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  6. Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability

    Article • IEEE Transactions on Device and Materials Reliability, June 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  7. On Transistor Sizing of CMOS 6T-SRAM for NBTI-aware Design

    Article • IET Circuits Devices & Systems, February 2020, the Institution of Engineering and Technology (the IET)

    Pr Hamid Bentarzi, Dr. Boualem Djezzar, Amel Chenouf, Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  8. Impact of Fin Height on Bias Temperature Instability of Memory Periphery FinFETs

    Article • October 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  9. Analysis of NBTI Degradation in nMOS-Capacitors and nMOSFETs

    Article • IEEE Transactions on Device and Materials Reliability, December 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  10. Experimental Investigation of NBTI Degradation in Power VDMOS Transistors Under Low Magnetic Field

    Article • IEEE Transactions on Device and Materials Reliability, March 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  11. On the Circuit-Level Reliability Degradation Due to AC NBTI Stress

    Article • IEEE Transactions on Device and Materials Reliability, September 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  12. On the turn-around phenomenon in n-MOS transistors under NBTI conditions

    Article • Solid-State Electronics, July 2016, Elsevier

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  13. Charge Pumping, Geometric Component, and Degradation Parameter Extraction in MOSFET Devices

    Article • IEEE Transactions on Device and Materials Reliability, December 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  14. Using the charge pumping geometric component to extract NBTI induced mobility degradation

    Article • October 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  15. NBTI stress on power VDMOS transistors under low magnetic field

    Article • October 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  16. Deep Analysis of the Geometric Component in Charge Pumping of Polycrystalline Silicon Thin-Film Transistors

    Article • IEEE Transactions on Electron Devices, October 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  17. On the permanent component profiling of the negative bias temperature instability in p-MOSFET devices

    Article • Solid-State Electronics, April 2015, Elsevier

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  18. Investigation of defect microstructures responsible for NBTI degradation using effective dipole moment extraction

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  19. Reaction-diffusion model for interface traps induced by BTS stress including H+, H and H2 as diffusion species

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  20. Reliability analysis of CMOS inverter subjected to AC & DC NBTI stresses

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  21. Does NBTI effect in MOS transistors depend on channel length?

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  22. Investigation of NBTI degradation on power VDMOS transistors under magnetic field

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  23. An Accurate Combination of on-the-fly Interface Trap and Threshold Voltage Methods for NBTI Degradation Extraction

    Article • Journal of Electronic Testing, August 2014, Springer Science + Business Media

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  24. Investigation of interface, shallow and deep oxide traps under NBTI stress using charge pumping technique

    Article • Microelectronics Reliability, May 2014, Elsevier

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  25. Investigating the NBTI effect on P- and N-substrate MOS capacitors and p-MOSFET transistors

    Article • December 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  26. On the permanent components of negative bias temperature instability

    Article • December 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  27. A new procedure for eliminating the geometric component from charge pumping: Application for NBTI and radiation issues

    Article • Microelectronics Reliability, April 2013, Elsevier

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  28. A propagation concept of negative bias temperature instability along the channel length in p-type metal oxide field effect transistor

    Article • Solid-State Electronics, April 2013, Elsevier

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  29. A new eye on NBTI-induced traps up to device lifetime using on the fly oxide trap method

    Article • December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  30. A novel method based on capacitance-voltage for negative bias temperatures instability studies: Concept and results

    Article • December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  31. An accurate extraction methodology for NBTI induced degradation using charge pumping based methods

    Article • December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  32. Deep experimental investigation of NBTI impact on CMOS inverter reliability

    Article • December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  33. Oxide trap annealing by H2 cracking at E' center under NBTI stress

    Article • December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  34. A New Method for Negative Bias Temperature Instability Assessment in P-Channel Metal Oxide Semiconductor Transistors

    Article • Japanese Journal of Applied Physics, November 2012, Institute of Physics Publishing

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  35. Does PMOS Vth shift wholly capture the degradation of CMOS inverter circuit under DC NBTI?

    Article • October 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  36. On-the-fly extraction method for interface-, oxide- trap and mobility degradation induced by NBTI stress

    Article • October 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  37. Two-point capacitance-voltage (TPCV) concept: A new method for NBTI characterization

    Article • October 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  38. On the fly oxide trap (otfot) concept: A new method for bias temperature instability characterization

    Article • July 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  39. Fast and simple method for estimation and separation of radiation-induced traps in MOSFETs devices

    Article • September 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  40. Geometric-component modeling in charge-pumping technique

    Article • July 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  41. Geometric Component in Constant-Amplitude Charge-Pumping Characteristics of LOCOS- and LDD-MOSFET Devices

    Article • IEEE Transactions on Device and Materials Reliability, March 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  42. Modeling and Simulation of Charge-Pumping Characteristics for LDD-MOSFET Devices With LOCOS Isolation

    Article • IEEE Transactions on Electron Devices, November 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  43. Radiation Effect Evaluation in Effective Short and Narrow Channels of LDD Transistor With LOCOS Isolation Using OTCP Method

    Article • IEEE Transactions on Device and Materials Reliability, March 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  44. Using Oxide-Trap Charge-Pumping Method in Radiation-Reliability Analysis of Short Lightly Doped Drain Transistor

    Article • IEEE Transactions on Device and Materials Reliability, March 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  45. Using Oxide-Trap Charge-Pumping method in radiation reliability analysis of short lightly doped drain transistor

    Article • September 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  46. Why Is Oxide-Trap Charge-Pumping Method Appropriate for Radiation-Induced Trap Depiction in MOSFET?

    Article • IEEE Transactions on Device and Materials Reliability, June 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  47. Oxide-trap charge-pumping for radiation reliability issue in MOS devices

    Article • April 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  48. Why is oxide-trap charge-pumping (OTCP) method appropriate for extracting the radiation-induced traps in mosfet?

    Article • January 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  49. Comparison Between OTCP and C-V Extraction Methods for Radiation-Induced Traps in MOSFET Devices

    Article • November 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  50. Field Acceleration Model for TDDB: Still a Valid Tool to Study the Reliability of Thick $\hbox{SiO}_{2}$-Based Dielectric Layers?

    Article • IEEE Transactions on Electron Devices, July 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  51. Automated MOS transistor degradation measurements based on labVIEW

    Article • January 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  52. Investigation of gate oxide thickness effect on the radiation-induced traps in MOSFET devices using OTCP method

    Article • January 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  53. A comparative study of different contact resistance test structures dedicated to the power process technology

    Article • Solid-State Electronics, October 2005, Elsevier

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  54. A new oxide-trap based on charge-pumping (OTCP) extraction method for irradiated MOSFET devices: part II (low frequencies)

    Article • IEEE Transactions on Nuclear Science, August 2004, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  55. A new oxide-trap based on charge-pumping (OTCP) extraction method for irradiated MOSFET devices: part I (high frequencies)

    Article • IEEE Transactions on Nuclear Science, August 2004, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  56. Extended Oxide-Trap extraction method to low frequencies for irradiated MOS transistors

    Article • January 2003, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  57. New oxide-trap extraction method for irradiated MOSFET devices at high frequencies

    Article • January 2003, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  58. On the correlation between radiation-induced oxide- and border-trap effects in the gate-oxide nMOSFET’s

    Article • Microelectronics Reliability, December 2002, Elsevier

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  59. Channel-length impact on radiation-induced threshold-voltage shift in N-MOSFET devices at low gamma ray radiation doses

    Article • IEEE Transactions on Nuclear Science, January 2000, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  60. Electrical characterization of oxide and Si/SiO/sub 2/ interface of irradiated NMOS transistors at low radiation doses

    Article • IEEE Transactions on Nuclear Science, January 1999, Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar

  61. Electrical characterization of oxide and Si/SiO/sub 2/ interface of irradiated NMOS transistors at low radiation doses

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability Boualem Djezzar