All Stories

  1. μ-ORCA: Optimizing Acceleration for Microsecond-Scale Deep Neural Network Inference on ACAP
  2. DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration
  3. To Overlay or to Customize? Revisiting Architectural Choices in Heterogeneous Systems
  4. Advancing Environmental Sustainability in Data Centers via Carbon Depreciation Models
  5. A Survey on Graph Neural Network Acceleration: Algorithms, Systems, and Customized Hardware
  6. AgRefactor: Refactoring for HLS Compatibility with a Self-Evolving Agentic Workflow
  7. AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration
  8. Holistic Optimization Framework for FPGA Accelerators
  9. MTrain: Enable Efficient CNN Training on Heterogeneous FPGA-Based Edge Servers
  10. ART: Customizing Accelerators for DNN-Enabled Real-Time Safety-Critical Systems
  11. Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks
  12. Reaction Latency Analysis of Message Synchronization in Edge-assisted Autonomous Driving
  13. Invited: Coping with Interconnects
  14. Using a multilevel framework to solve quantum layout synthesis problem.
  15. Stream-HLS: Towards Automatic Dataflow Acceleration
  16. ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines
  17. A Unified Framework for Automated Code Transformation and Pragma Insertion
  18. InTRRA: Inter-Task Resource-Repurposing Accelerator for Efficient Transformer Inference on FPGAs
  19. SAT-Accel: A Modern SAT Solver on a FPGA
  20. Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal Scheduling
  21. Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach
  22. FiberFlex: FPGA-based Intelligent & Distributed Fiber Sensor System for Pedestrian Recognition
  23. Amortizing Embodied Carbon Across Generations
  24. CHEF: A Framework for Deploying Heterogeneous Models on Clusters With Heterogeneous FPGAs
  25. EQ-ViT: Algorithm-Hardware Co-Design for End-to-End Acceleration of Real-Time Vision Transformer Inference on Versal ACAP Architecture
  26. Efficient Task Transfer for HLS DSE
  27. Quantum State Preparation Circuit Optimization Exploiting Don't Cares
  28. GNN-Based Performance Prediction of Quantum Optimization of Maximum Independent Set
  29. RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis
  30. Reducing Smart Phone Environmental Footprints with In-Memory Processing
  31. Learning to Compare Hardware Designs for High-Level Synthesis
  32. Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis
  33. PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
  34. CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture
  35. SCARIF: Towards Carbon Modeling of Cloud Servers with Accelerators
  36. Q-Pilot: Field Programmable Qubit Array Compilation with Flying Ancillas
  37. Enabling On-Device Large Language Model Personalization with Self-Supervised Data Selection and Synthesis
  38. SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering
  39. TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs
  40. Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach
  41. SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
  42. FPGA-based Accelerator for Sparse Triangular Solver
  43. Scheduling and Physical Design
  44. Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets
  45. REFRESH FPGAs: Sustainable FPGA Chiplet Architectures
  46. AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP
  47. Efficient Hardware and Software Design for On-device Learning
  48. TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design
  49. Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
  50. NeSSA: Near-Storage Data Selection for Accelerated Machine Learning Training
  51. High Performance, Low Power Matrix Multiply Design on ACAP: from Architecture, Design Challenges and DSE Perspectives
  52. Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition
  53. Scalable Optimal Layout Synthesis for NISQ Quantum Processors
  54. Lightning Talk: Scaling Up Quantum Compilation – Challenges and Opportunities
  55. A Comprehensive Automated Exploration Framework for Systolic Array Designs
  56. RapidStream 2.0: Automated Parallel Implementation of Latency Insensitive FPGA Designs Through Partial Reconfiguration
  57. FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis
  58. FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA
  59. HMLib: Efficient Data Transfer for HLS Using Host Memory
  60. Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver
  61. CHARM: C omposing H eterogeneous A ccele R ators for M atrix Multiply on Versal ACAP Architecture
  62. Sustainable AI Processing at the Edge
  63. FPGA HLS Today: Successes, Challenges, and Opportunities
  64. Enabling Weakly Supervised Temporal Action Localization From On-Device Learning of the Video Stream
  65. Qubit Mapping for Reconfigurable Atom Arrays
  66. OverGen: Improving FPGA Usability through Domain-specific Overlay Generation
  67. EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization
  68. Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction
  69. N-DISE
  70. AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
  71. Serpens
  72. Automated accelerator optimization aided by graph neural networks
  73. Improving GNN-based accelerator design automation with meta learning
  74. H2H
  75. Automated Accelerator Optimization Aided by Graph Neural Networks
  76. SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation
  77. Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication
  78. Accelerating SSSP for Power-Law Graphs
  79. RapidStream
  80. Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices
  81. TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation
  82. AutoBridge
  83. Extending High-Level Synthesis for Task-Parallel Programs
  84. HBM Connect: High-Performance HLS Interconnect for FPGA HBM
  85. MOCHA
  86. AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators
  87. AutoSA
  88. BLINK
  89. HeteroRefactor
  90. Bonsai: High-Performance Adaptive Merge Tree Sorting
  91. Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit
  92. Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
  93. Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management
  94. Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis
  95. LANMC
  96. HeteroCL
  97. Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment
  98. HLS-based optimization and design space exploration for applications with variable loop bounds
  99. PolySA
  100. SODA
  101. TGPA
  102. Doppio: I/O-Aware Performance Analysis, Modeling and Optimization for In-memory Computing Framework
  103. ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA
  104. Latte: Locality Aware Transformation for High-Level Synthesis
  105. CPU-FPGA Co-Optimization for Big Data Applications
  106. Bandwidth Optimization Through On-Chip Memory Restructuring for HLS
  107. Caffeine
  108. Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
  109. Invited - Heterogeneous datacenters
  110. Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication
  111. ARAPrototyper
  112. InterFS
  113. CMOST
  114. On-chip interconnection network for accelerator-rich architectures
  115. A Fully Pipelined and Dynamically Composable Architecture of CGRA
  116. Automatic memory partitioning and scheduling for throughput and power optimization