All Stories

  1. AceRoute: Adaptive Compute-Efficient FPGA Routing with Pluggable Intra-Connection Bidirectional Exploration
  2. G2PM: Performance Modeling for ACAP Architecture with Dual-Tiered Graph Representation Learning
  3. PT-Map: Efficient Program Transformation Optimization for CGRA Mapping
  4. PONO: Power Optimization with Near Optimal SMT-based Sub-circuit Generation
  5. Incremental SAT-based Exact Synthesis
  6. RF-SIFTER: Sifting Signals at Layer-0.5 to Mitigate Wideband Cross-Technology Interference for IoT
  7. GDSII-Guard: ECO Anti-Trojan Optimization with Exploratory Timing-Security Trade-Offs
  8. Weave: Abstraction for Accelerator Integration of Generated Modules
  9. An Intermediate-Centric Dataflow for Transposed Convolution Acceleration on FPGA
  10. ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs
  11. EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper)
  12. BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices
  13. Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping
  14. Dual-output LUT merging during FPGA technology mapping
  15. FTConv
  16. Adaptive-precision framework for SGD using deep Q-learning
  17. A Parallel Bandit-Based Approach for Autotuning FPGA Compilation
  18. Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
  19. Analytical Clustering Score with Application to Postplacement Register Clustering
  20. Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging