All Stories

  1. From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR
  2. Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device
  3. Cypress: VLSI-Inspired PCB Placement with GPU Acceleration
  4. ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines
  5. Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference
  6. Allo: A Programming Model for Composable Accelerator Design
  7. A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs
  8. Formal Verification of Source-to-Source Transformations for HLS
  9. Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator
  10. RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm
  11. Accelerator design with decoupled hardware customizations
  12. HeteroFlow
  13. RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms