All Stories

  1. Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device
  2. Cypress: VLSI-Inspired PCB Placement with GPU Acceleration
  3. ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines
  4. Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference
  5. Allo: A Programming Model for Composable Accelerator Design
  6. A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs
  7. Formal Verification of Source-to-Source Transformations for HLS
  8. Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator
  9. RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm
  10. Accelerator design with decoupled hardware customizations
  11. HeteroFlow
  12. RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms