All Stories

  1. Low-Cost Robust Anti-Removal Logic for Protecting Functionally Obfuscated DSP core against Removal Attack

    Article • Electronics Letters, February 2019, the Institution of Engineering and Technology (the IET)

    Professor Anirban Sengupta

  2. Effect of NBTI Stress on DSP cores used in CE Devices: Threat Model and Performance Estimation

    Article • IET Computers & Digital Techniques, September 2018, the Institution of Engineering and Technology (the IET)

    Professor Anirban Sengupta

  3. Protecting an Intellectual Property Core during Architectural Synthesis using High-Level Transformation Based Obfuscation

    Article • Electronics Letters, May 2017, the Institution of Engineering and Technology (the IET)

    Professor Anirban Sengupta, Dr. Dipanjan Roy

  4. Low Cost Security Aware High Level Synthesis Methodology

    Article • IET Computers & Digital Techniques, September 2016, the Institution of Engineering and Technology (the IET)

    Professor Anirban Sengupta

  5. Intellectual property core protection of control data flow graphs using robust watermarking during behavioural synthesis based on user resource constraint and loop unrolling factor

    Article • Electronics Letters, March 2016, the Institution of Engineering and Technology (the IET)

    Professor Anirban Sengupta

  6. Untrusted Third Party Digital IP Cores

    Article • May 2015, ACM (Association for Computing Machinery)

    Professor Anirban Sengupta

  7. Exploration of k c-cycle transient fault-secured datapath and loop unrolling factor for control data flow graphs during high-level synthesis

    Article • Electronics Letters, April 2015, the Institution of Engineering and Technology (the IET)

    Professor Anirban Sengupta

  8. Swarm-inspired exploration of architecture and unrolling factors for nested-loop-based application in architectural synthesis

    Article • Electronics Letters, January 2015, the Institution of Engineering and Technology (the IET)

    Professor Anirban Sengupta

  9. Particle Swarm Optimisation Driven Low Cost Single Event Transient Fault Secured Design during Architectural Synthesis (Invited Paper)

    Article • The Journal of Engineering, February 2009, the Institution of Engineering and Technology (the IET)

    Professor Anirban Sengupta