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  1. PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis

    Article • ACM Transactions on Design Automation of Electronic Systems, October 2024, ACM (Association for Computing Machinery)

    Dr. Dipanjan Roy

  2. Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware

    Article • IEEE Transactions on Consumer Electronics, August 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  3. Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering [Hardware Matter]

    Article • IEEE Consumer Electronics Magazine, May 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  4. Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, April 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  5. Multi-phase watermark for IP core protection

    Article • January 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  6. Reusable intellectual property core protection for both buyer and seller

    Article • January 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  7. Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters]

    Article • IEEE Consumer Electronics Magazine, January 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  8. A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC

    Article • IEEE Access, January 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  9. Low Cost Functional Obfuscation of Reusable IP Cores used in CE Hardware through Robust Locking

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  10. Mathematical Validation of HWT Based Lossless Image Compression

    Article • December 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  11. DSP design protection in CE through algorithmic transformation based structural obfuscation

    Article • IEEE Transactions on Consumer Electronics, November 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  12. Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools

    Article • Advances in Engineering Software, August 2017, Elsevier

    Dr. Dipanjan Roy

  13. Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis

    Article • Future Generation Computer Systems, June 2017, Elsevier

    Dr. Dipanjan Roy

  14. Protecting an Intellectual Property Core during Architectural Synthesis using High-Level Transformation Based Obfuscation

    Article • Electronics Letters, May 2017, the Institution of Engineering and Technology (the IET)

    Professor Anirban Sengupta, Dr. Dipanjan Roy

  15. Enhancing Saliency of an Object Using Genetic Algorithm

    Article • May 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  16. Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters]

    Article • IEEE Consumer Electronics Magazine, April 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Dipanjan Roy

  17. Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper)

    Article • Integration, September 2016, Elsevier

    Dr. Dipanjan Roy