All Stories

  1. Refined Two-Sided Learning Rate Tuning for Robust Evaluation in Federated Learning

    Article • IEEE Transactions on Artificial Intelligence, February 2026, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  2. FedAGF: Adaptive Concurrency via Gradient Feedback for Mitigating Extreme Label Skew in Budget-Constrained Federated Learning

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, January 2026, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  3. Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference

    Article • Sensors, February 2023, MDPI AG

    Andrea Calimera

  4. Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays

    Article • IEEE Internet of Things Journal, January 2023, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  5. Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning

    Article • IEEE Internet of Things Journal, January 2023, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  6. Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks

    Article • ACM Transactions on Embedded Computing Systems, July 2022, ACM (Association for Computing Machinery)

    Andrea Calimera, Massimo Poncino

  7. Monocular Depth Perception on Microcontrollers for Edge Applications

    Article • IEEE Transactions on Circuits and Systems for Video Technology, March 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  8. Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs

    Article • IEEE Internet of Things Journal, January 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  9. Communication-Efficient Federated Learning with Gradual Layer Freezing

    Article • IEEE Embedded Systems Letters, January 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  10. Dynamic ConvNets on Tiny Devices via Nested Sparsity

    Article • IEEE Internet of Things Journal, January 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  11. AxP: A HW-SW Co-Design Pipeline for Energy-Efficient Approximated ConvNets via Associative Matching

    Article • Applied Sciences, November 2021, MDPI AG

    Andrea Calimera

  12. ACME: An Energy-Efficient Approximate Bus Encoding for I2C

    Article • July 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera, Massimo Poncino

  13. Ultra-compact binary neural networks for human activity recognition on RISC-V processors

    Article • May 2021, ACM (Association for Computing Machinery)

    Massimo Poncino, Andrea Calimera

  14. TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, February 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  15. Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools

    Article • Proceedings of the IEEE, January 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  16. EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets

    Article • August 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  17. TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks

    Article • August 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  18. Efficacy of Topology Scaling for Temperature and Latency Constrained Embedded ConvNets

    Article • Journal of Low Power Electronics and Applications, March 2020, MDPI AG

    Andrea Calimera

  19. Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, February 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  20. Corrigendum to“Approximate error detection-correction for efficient adaptive voltage Over-Scaling”[Integration 63 (2018) 220–231]

    Article • Integration, January 2020, Elsevier

    Andrea Calimera

  21. Fast and Accurate Inference on Microcontrollers With Boosted Cooperative Convolutional Neural Networks (BC-Net)

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, January 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  22. Performance Profiling of Embedded ConvNets under Thermal-Aware DVFS

    Article • Electronics, November 2019, MDPI AG

    Andrea Calimera

  23. CoopNet: Cooperative Convolutional Neural Network for Low-Power MCUs

    Article • November 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  24. Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores

    Article • November 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  25. Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors

    Article • October 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  26. Inference on the Edge: Performance Analysis of an Image Classification Task Using Off-The-Shelf CPUs and Open-Source ConvNets

    Article • October 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  27. Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection

    Article • Journal of Low Power Electronics and Applications, April 2019, MDPI AG

    Andrea Calimera

  28. Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms

    Article • March 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  29. Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse

    Article • March 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  30. SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars

    Article • March 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  31. Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores

    Article • IEEE Access, January 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  32. Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis

    Article • January 2019, Springer Science + Business Media

    Andrea Calimera

  33. On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling

    Article • January 2019, Springer Science + Business Media

    Andrea Calimera

  34. Layer-Wise Compressive Training for Convolutional Neural Networks

    Article • Future Internet, December 2018, MDPI AG

    Andrea Calimera, Matteo Grimaldi

  35. Logic-In-Memory Architecture For Min/Max Search

    Article • December 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  36. Adaptive Convolutional Neural Networks

    Article • November 2018, ACM (Association for Computing Machinery)

    Andrea Calimera, Valentino Peluso

  37. Energy-Driven Precision Scaling for Fixed-Point ConvNets

    Article • October 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  38. Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits

    Article • October 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  39. Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling

    Article • Integration, September 2018, Elsevier

    Andrea Calimera

  40. Quasi-exact logic functions through classification trees

    Article • Integration, September 2018, Elsevier

    Andrea Calimera

  41. Weak-MAC: Arithmetic Relaxation for Dynamic Energy-Accuracy Scaling in ConvNets

    Article • May 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Valentino Peluso, Andrea Calimera

  42. Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS

    Article • May 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Valentino Peluso, Andrea Calimera, Dr. Mario R. Casu

  43. Multiplication by Inference using Classification Trees: A Case-Study Analysis

    Article • May 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  44. All-digital embedded meters for on-line power estimation

    Article • March 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Valentino Peluso, Andrea Calimera

  45. Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator

    Article • March 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Valentino Peluso, Andrea Calimera

  46. A compression-driven training framework for embedded deep neural networks

    Article • January 2018, ACM (Association for Computing Machinery)

    Matteo Grimaldi, Andrea Calimera

  47. Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS

    Article • October 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Valentino Peluso, Andrea Calimera

  48. Activation-Kernel Extraction through Machine Learning

    Article • September 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  49. Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling

    Article • September 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  50. Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping

    Article • January 2017, Springer Science + Business Media

    Valentino Peluso, Andrea Calimera

  51. Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits

    Article • January 2017, Springer Science + Business Media

    Andrea Calimera

  52. Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, December 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  53. Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs

    Article • September 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Valentino Peluso, Andrea Calimera

  54. Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits

    Article • September 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  55. Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies

    Article • May 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  56. Graphene-PLA (GPLA)

    Article • January 2016, ACM (Association for Computing Machinery)

    Andrea Calimera

  57. Ultra-low power circuits using graphene p–n junctions and adiabatic computing

    Article • Microprocessors and Microsystems, November 2015, Elsevier

    Andrea Calimera

  58. An automated design flow for approximate circuits based on reduced precision redundancy

    Article • October 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  59. One-pass logic synthesis for graphene-based Pass-XNOR logic circuits

    Article • June 2015, ACM (Association for Computing Machinery)

    Andrea Calimera, Massimo Poncino

  60. Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores

    Article • May 2015, ACM (Association for Computing Machinery)

    Andrea Calimera, Massimo Poncino, Yukai Chen

  61. Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions

    Article • May 2015, ACM (Association for Computing Machinery)

    Andrea Calimera, Massimo Poncino

  62. Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization

    Article • May 2015, ACM (Association for Computing Machinery)

    Andrea Calimera, Massimo Poncino, Professor Giovanni De Micheli

  63. Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs

    Article • January 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  64. Power-Gating for Leakage Control and Beyond

    Article • October 2014, Springer Science + Business Media

    Andrea Calimera

  65. Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates

    Article • August 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  66. Modeling of Physical Defects in PN Junction Based Graphene Devices

    Article • Journal of Electronic Testing, June 2014, Springer Science + Business Media

    Andrea Calimera

  67. Row-based body-bias assignment for dynamic thermal clock-skew compensation

    Article • Microelectronics Journal, May 2014, Elsevier

    Andrea Calimera

  68. Dynamic Indexing: Leakage-Aging Co-Optimization for Caches

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, February 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  69. Pass-XNOR logic: A new logic style for P-N junction based graphene circuits

    Article • January 2014, EDAA

    Andrea Calimera

  70. Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs

    Article • Microelectronics Journal, November 2013, Elsevier

    Andrea Calimera

  71. Power modeling and characterization of Graphene-based logic gates

    Article • September 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  72. Exploration of different implementation styles for graphene-based reconfigurable gates

    Article • May 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  73. Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices

    Article • April 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  74. Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs

    Article • April 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  75. Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, March 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  76. Delay model for reconfigurable logic gates based on graphene PN-junctions

    Article • January 2013, ACM (Association for Computing Machinery)

    Andrea Calimera

  77. Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints

    Article • January 2013, ACM (Association for Computing Machinery)

    Andrea Calimera

  78. On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture

    Article • January 2013, Springer Science + Business Media

    Andrea Calimera

  79. Design Techniques and Architectures for Low-Leakage SRAMs

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, September 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  80. Design Techniques for NBTI-Tolerant Power-Gating Architectures

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, April 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  81. NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems

    Article • Journal of Electronic Testing, April 2012, Springer Science + Business Media

    Andrea Calimera

  82. Energy-optimal caches with guaranteed lifetime

    Article • January 2012, ACM (Association for Computing Machinery)

    Andrea Calimera

  83. NBTI effects on tree-like clock distribution networks

    Article • January 2012, ACM (Association for Computing Machinery)

    Andrea Calimera

  84. On-chip process variation-tracking through an all-digital monitoring architecture

    Article • IET Circuits Devices & Systems, January 2012, the Institution of Engineering and Technology (the IET)

    Andrea Calimera

  85. Power Efficient Variability Compensation Through Clustered Tunable Power-Gating

    Article • IEEE Journal on Emerging and Selected Topics in Circuits and Systems, September 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  86. A new Built-In Current Sensor scheme to detect dynamic faults in Nano-Scale SRAMs

    Article • March 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  87. NBTI-aware data allocation strategies for scratchpad memory based embedded systems

    Article • March 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  88. An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs

    Article • January 2011, Springer Science + Business Media

    Andrea Calimera

  89. Buffering of frequent accesses for reduced cache aging

    Article • January 2011, ACM (Association for Computing Machinery)

    Andrea Calimera

  90. Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating

    Article • January 2011, Springer Science + Business Media

    Andrea Calimera

  91. NBTI-Aware Clustered Power Gating

    Article • ACM Transactions on Design Automation of Electronic Systems, November 2010, ACM (Association for Computing Machinery)

    Andrea Calimera

  92. Temperature-Insensitive Dual-$V_{\rm th}$ Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, November 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  93. Dual- assignment policies in ITD-aware synthesis

    Article • Microelectronics Journal, September 2010, Elsevier

    Andrea Calimera

  94. Analysis of NBTI-induced SNM degradation in power-gated SRAM cells

    Article • May 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  95. Aging effects of leakage optimizations for caches

    Article • January 2010, ACM (Association for Computing Machinery)

    Andrea Calimera

  96. An integrated thermal estimation framework for industrial embedded platforms

    Article • January 2010, ACM (Association for Computing Machinery)

    Andrea Calimera

  97. Dynamic indexing

    Article • January 2010, ACM (Association for Computing Machinery)

    Andrea Calimera

  98. Generating power-hungry test programs for power-aware validation of pipelined processors

    Article • January 2010, ACM (Association for Computing Machinery)

    Andrea Calimera

  99. On-chip Thermal Modeling Based on SPICE Simulation

    Article • January 2010, Springer Science + Business Media

    Andrea Calimera

  100. Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering

    Article • January 2010, Springer Science + Business Media

    Andrea Calimera

  101. Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, September 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  102. NBTI-aware power gating for concurrent leakage and aging optimization

    Article • August 2009, ACM (Association for Computing Machinery)

    Andrea Calimera

  103. Placement-aware clustering for integrated clock and power gating

    Article • May 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Massimo Poncino, Andrea Calimera

  104. NBTI-aware sleep transistor design for reliable power-gating

    Article • January 2009, ACM (Association for Computing Machinery)

    Andrea Calimera

  105. Thermal-Aware Design Techniques for Nanometer CMOS Circuits

    Article • Journal of Low Power Electronics, December 2008, American Scientific Publishers

    Andrea Calimera

  106. Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis

    Article • September 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  107. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits

    Article • May 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  108. Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints

    Article • March 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  109. Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits

    Article • January 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  110. Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits

    Article • January 2008, ACM (Association for Computing Machinery)

    Andrea Calimera

  111. Temperature-insensitive synthesis using multi-vt libraries

    Article • January 2008, ACM (Association for Computing Machinery)

    Andrea Calimera

  112. Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing

    Article • April 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Andrea Calimera

  113. Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology

    Article • January 2007, ACM (Association for Computing Machinery)

    Andrea Calimera