All Stories

  1. NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming
  2. Enhanced Machine-Learning Flow for Microwave-Sensing Systems for Contaminant Detection in Food
  3. Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark
  4. High-Level Design of Precision-Scalable DNN Accelerators Based on Sum-Together Multipliers
  5. To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration
  6. Accelerating Quantized DNN Layers on RISC-V with a STAR MAC Unit
  7. A Reconfigurable Multiplier/Dot-Product Unit for Precision-Scalable Deep Learning Applications
  8. Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops
  9. Brain Stroke Classification via Machine Learning Algorithms Trained with a Linearized Scattering Operator
  10. Physical Contamination Detection in Food Industry Using Microwave and Machine Learning
  11. Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms
  12. Efficient Training and Hardware Co-design of Machine Learning Models
  13. Machine-Learning-Based Microwave Sensing: A Case Study for the Food Industry
  14. Experimental Validation of a Microwave System for Brain Stroke 3-D Imaging
  15. CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms
  16. FPGA Acceleration of 3D FDTD for Multi- Antennas Microwave Imaging Using HLS
  17. High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs
  18. Power-Optimal Mapping of CNN Applications to Cloud-Based Multi-FPGA Platforms
  19. Noninvasive Inline Food Inspection via Microwave Imaging Technology: An Application Example in the Food Industry
  20. A Prototype Microwave System for 3D Brain Stroke Imaging
  21. High Level Design of a Flexible PCA Hardware Accelerator Using a New Block-Streaming Method
  22. Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms
  23. Design and Experimental Assessment of a 2D Microwave Imaging System for Brain Stroke Monitoring
  24. Low-Cost Low-Power Acceleration of a Microwave Imaging Algorithm for Brain Stroke Monitoring
  25. Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS
  26. Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers
  27. State-of-the-Art Power Management Circuits for Piezoelectric Energy Harvesters
  28. Power-performance assessment of different DVFS control policies in NoCs
  29. A COTS-Based Microwave Imaging System for Breast-Cancer Detection
  30. Accelerators for Breast Cancer Detection
  31. Microwave Imaging for Breast Cancer Detection: A COTS-Based Prototype
  32. A synchronous latency-insensitive RISC for better than worst-case design
  33. Rate-Based vs Delay-Based Control for DVFS in NoC
  34. Simulation and design of an UWB imaging system for breast cancer detection
  35. UWB microwave imaging for breast cancer detection
  36. Accelerator Memory Reuse in the Dark Silicon Era
  37. Power‐gating technique for network‐on‐chip buffers
  38. Joint delay and power control in single-server queueing systems
  39. LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS
  40. UWB receiver for breast cancer detection: Comparison between two different approaches
  41. Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection
  42. Breast cancer detection based on an UWB imaging system: Receiver design and simulations
  43. Exploiting space diversity and Dynamic Voltage Frequency Scaling in multiplane Network-on-Chips
  44. DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems
  45. Half-buffer retiming and token cages for synchronous elastic circuits
  46. A NoC-based hybrid message-passing/shared-memory approach to CMP design
  47. A flexible UWB Transmitter for breast cancer detection imaging systems
  48. MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture
  49. Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming
  50. Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis
  51. A Fully Differential Digital CMOS UWB Pulse Generator
  52. A Case Study for NoC-Based Homogeneous MPSoC Architectures
  53. A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design
  54. A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver
  55. The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology
  56. Adaptive Latency-Insensitive Protocols
  57. A Low-power CMOS 2-PPM Demodulator for Energy Detection IR-UWB Receivers
  58. An effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal UWB System-on-Chip
  59. Floorplanning With Wire Pipelining in Adaptive Communication Channels
  60. Throughput-driven floorplanning with wire pipelining
  61. Implementation aspects of a transmitted-reference UWB receiver
  62. Effects of temperature in deep-submicron global interconnect optimization in future technology nodes
  63. An electromigration and thermal model of power wires for a priori high-level reliability prediction
  64. Floorplanning for throughput
  65. A new approach to latency insensitive design
  66. Coupled electro-thermal modeling and optimization of clock networks
  67. A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization
  68. Effects of Temperature in Deep-Submicron Global Interconnect Optimization
  69. Reduced clock swing domino logic
  70. History effect characterization in PD-SOI CMOS gates
  71. Clock Distribution Network Optimization under Self-Heating and Timing Constraints
  72. Synthesis of low-leakage PD-SOI circuits with body-biasing
  73. A New System Design Methodology for Wire Pipelined SoC
  74. A multiprocessor based packet-switch: performance analysis of the communication infrastructure
  75. Energy detection UWB receiver design using a multi-resolution VHDL-AMS description
  76. Converting an embedded low-power SRAM from bulk to PD-SOI
  77. A high accuracy-low complexity model for CMOS delays