All Stories

  1. ConfiBench: Automatic Testbench Generation with Confidence-Based Scenario Mask and Testbench Ensemble using LLMs for HDL Design
  2. Special Sessions - Hardware-Software Co-Design for Machine Learning Systems Made Open-Source
  3. HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis
  4. Process-Variation-Aware Design Optimization for Wavelength-Routed Optical Networks-on-Chip
  5. iG-kway: Incremental k-way Graph Partitioning on GPU
  6. FT-MUX: A Fault-Tolerant Microfluidic Multiplexer Design
  7. CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-Chip
  8. An Efficient General-Purpose Optical Accelerator for Neural Networks
  9. Dynamic Topology-Aware Flow Path Construction and Scheduling Optimization for Multilayered Continuous-Flow Microfluidic Biochips
  10. A Backup Resource Customization and Allocation Method for Wavelength-Routed Optical Networks-on-Chip Topologies
  11. 3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric Control
  12. HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner
  13. BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks
  14. Minimizing Worst-Case Data Transmission Cycles in Wavelength-Routed Optical NoC through Bandwidth Allocation
  15. RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics
  16. AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design
  17. Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models
  18. Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
  19. Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip
  20. LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
  21. muRISCV-NN: Challenging Zve32x Autovectorization with TinyML Inference Library for RISC-V Vector Extension
  22. Logic Design of Neural Networks for High-Throughput and Low-Power Applications
  23. MLonMCU: TinyML Benchmarking with Fast Retargeting
  24. Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM's UMA
  25. PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration
  26. GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates
  27. SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips
  28. FXT-Route
  29. CompaSeC
  30. Training PPA Models for Embedded Memories on a Low-data Diet
  31. CoMUX
  32. An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors
  33. GNN-based concentration prediction for random microfluidic mixers
  34. Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip Systems
  35. Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level
  36. REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance
  37. A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs
  38. Light
  39. Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars
  40. PathDriver
  41. PSION 2
  42. Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks
  43. Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs
  44. Reliable and Robust RRAM-based Neuromorphic Computing
  45. MiniControl
  46. Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML
  47. CustomTopo
  48. Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips
  49. Wavefront-MCTS
  50. Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCs
  51. Supporting Design of Embedded Software that is robust against Hardware Errors.
  52. A Method for Phase Noise Analysis of RF Circuits
  53. Model-based framework for networks-on-chip design space exploration
  54. From biochips to quantum circuits: computer-aided design for emerging technologies
  55. Where formal verification can help in functional safety analysis
  56. PieceTimer
  57. Control-fluidic CoDesign for paper-based digital microfluidic biochips
  58. PROTON+
  59. EffiTest
  60. Columba
  61. Dark silicon management: an integrated and coordinated cross-layer approach
  62. GRIP
  63. Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping
  64. Beyond GORDIAN and Kraftwerk
  65. Application-aware cross-layer reliability analysis and optimization
  66. Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs