All Stories

  1. Invited: Navigating the Frontier of Optimality and Complexity: Advanced Design Automation for Wavelength-Routed ONoCs
  2. ConfiBench: Automatic Testbench Generation with Confidence-Based Scenario Mask and Testbench Ensemble using LLMs for HDL Design
  3. Special Sessions - Hardware-Software Co-Design for Machine Learning Systems Made Open-Source
  4. HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis
  5. Process-Variation-Aware Design Optimization for Wavelength-Routed Optical Networks-on-Chip
  6. iG-kway: Incremental k-way Graph Partitioning on GPU
  7. FT-MUX: A Fault-Tolerant Microfluidic Multiplexer Design
  8. CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-Chip
  9. An Efficient General-Purpose Optical Accelerator for Neural Networks
  10. Dynamic Topology-Aware Flow Path Construction and Scheduling Optimization for Multilayered Continuous-Flow Microfluidic Biochips
  11. A Backup Resource Customization and Allocation Method for Wavelength-Routed Optical Networks-on-Chip Topologies
  12. 3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric Control
  13. HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner
  14. BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks
  15. Minimizing Worst-Case Data Transmission Cycles in Wavelength-Routed Optical NoC through Bandwidth Allocation
  16. RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics
  17. AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design
  18. Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models
  19. Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
  20. Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip
  21. LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
  22. muRISCV-NN: Challenging Zve32x Autovectorization with TinyML Inference Library for RISC-V Vector Extension
  23. Logic Design of Neural Networks for High-Throughput and Low-Power Applications
  24. MLonMCU: TinyML Benchmarking with Fast Retargeting
  25. Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM's UMA
  26. PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration
  27. GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates
  28. SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips
  29. FXT-Route
  30. CompaSeC
  31. Training PPA Models for Embedded Memories on a Low-data Diet
  32. CoMUX
  33. An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors
  34. GNN-based concentration prediction for random microfluidic mixers
  35. Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip Systems
  36. Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level
  37. REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance
  38. A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs
  39. Light
  40. Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars
  41. PathDriver
  42. PSION 2
  43. Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks
  44. Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs
  45. Reliable and Robust RRAM-based Neuromorphic Computing
  46. MiniControl
  47. Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML
  48. CustomTopo
  49. Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips
  50. Wavefront-MCTS
  51. Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCs
  52. Supporting Design of Embedded Software that is robust against Hardware Errors.
  53. A Method for Phase Noise Analysis of RF Circuits
  54. Model-based framework for networks-on-chip design space exploration
  55. From biochips to quantum circuits: computer-aided design for emerging technologies
  56. Where formal verification can help in functional safety analysis
  57. PieceTimer
  58. Control-fluidic CoDesign for paper-based digital microfluidic biochips
  59. PROTON+
  60. EffiTest
  61. Columba
  62. Dark silicon management: an integrated and coordinated cross-layer approach
  63. GRIP
  64. Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping
  65. Beyond GORDIAN and Kraftwerk
  66. Application-aware cross-layer reliability analysis and optimization
  67. Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs