All Stories

  1. muRISCV-NN: Challenging Zve32x Autovectorization with TinyML Inference Library for RISC-V Vector Extension

    Article • May 2024, ACM (Association for Computing Machinery)

    Philipp van Kempen, Ulf Schlichtmann, Dr Daniel Mueller-Gritschneder

  2. MLonMCU: TinyML Benchmarking with Fast Retargeting

    Article • September 2023, ACM (Association for Computing Machinery)

    Dr Daniel Mueller-Gritschneder, Ulf Schlichtmann, Philipp van Kempen

  3. Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM's UMA

    Article • September 2023, ACM (Association for Computing Machinery)

    Dr Daniel Mueller-Gritschneder, Ulf Schlichtmann, Philipp van Kempen

  4. vRTLmod

    Article • May 2023, ACM (Association for Computing Machinery)

    Dr Daniel Mueller-Gritschneder

  5. CompaSeC

    Article • January 2023, ACM (Association for Computing Machinery)

    Dr Daniel Mueller-Gritschneder, Ulf Schlichtmann

  6. An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors

    Article • ACM Transactions on Architecture and Code Optimization, September 2022, ACM (Association for Computing Machinery)

    Marcel Mettler, Dr Daniel Mueller-Gritschneder, Ulf Schlichtmann

  7. REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance

    Article • ACM Transactions on Embedded Computing Systems, October 2021, ACM (Association for Computing Machinery)

    Dr Daniel Mueller-Gritschneder, Ulf Schlichtmann

  8. Automated HW/SW co-design for edge AI

    Article • September 2021, ACM (Association for Computing Machinery)

    Dr Daniel Mueller-Gritschneder

  9. A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs

    Article • ACM Transactions on Architecture and Code Optimization, March 2021, ACM (Association for Computing Machinery)

    Marcel Mettler, Dr Daniel Mueller-Gritschneder, Ulf Schlichtmann

  10. Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs

    Article • ACM Transactions on Design Automation of Electronic Systems, October 2020, ACM (Association for Computing Machinery)

    Yong Hu, Dr Daniel Mueller-Gritschneder, Ulf Schlichtmann, Marcel Mettler

  11. Analysis of Losses in Modular Reconfigurable Energy Storage Systems by SystemC TLM / AMS

    Article • ACM Transactions on Design Automation of Electronic Systems, July 2019, ACM (Association for Computing Machinery)

    Dr Daniel Mueller-Gritschneder, Thomas Zimmermann

  12. Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML

    Article • November 2018, ACM (Association for Computing Machinery)

    Ulf Schlichtmann, Dr Daniel Mueller-Gritschneder

  13. Wavefront-MCTS

    Article • November 2018, ACM (Association for Computing Machinery)

    Yong Hu, Ulf Schlichtmann, Dr Daniel Mueller-Gritschneder

  14. Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCs

    Article • ACM Transactions on Design Automation of Electronic Systems, April 2018, ACM (Association for Computing Machinery)

    Dr Daniel Mueller-Gritschneder, Ulf Schlichtmann, Yong Hu

  15. Supporting Design of Embedded Software that is robust against Hardware Errors.

    Article • ACM Transactions on Embedded Computing Systems, January 2018, ACM (Association for Computing Machinery)

    Ulf Schlichtmann, Petra Kleeberger, Dr Daniel Mueller-Gritschneder

  16. Model-based framework for networks-on-chip design space exploration

    Article • January 2017, ACM (Association for Computing Machinery)

    Dr Daniel Mueller-Gritschneder, Yong Hu, Ulf Schlichtmann

  17. Host-Compiled Simulation

    Article • January 2017, Springer Science + Business Media

    Dr Daniel Mueller-Gritschneder

  18. The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping

    Article • January 2017, ACM (Association for Computing Machinery)

    Dr Daniel Mueller-Gritschneder

  19. Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models

    Article • December 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  20. Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing

    Article • January 2016, ACM (Association for Computing Machinery)

    Petra Kleeberger, Dr Daniel Mueller-Gritschneder

  21. Host-Compiled Simulation

    Article • January 2016, Springer Science + Business Media

    Dr Daniel Mueller-Gritschneder

  22. Embedded software reliability testing by unit-level fault injection

    Article • January 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  23. Automation of FPGA performance monitoring and debugging Using IP-XACT and graph-grammars

    Article • September 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  24. GRIP

    Article • June 2015, ACM (Association for Computing Machinery)

    Ulf Schlichtmann, Dr Daniel Mueller-Gritschneder

  25. Application-aware cross-layer reliability analysis and optimization

    Article • it - Information Technology, January 2015, De Gruyter

    Ulf Schlichtmann, Dr Daniel Mueller-Gritschneder

  26. The Next Generation of Virtual Prototyping: Ultra-Fast Yet Accurate Simulation of HW/SW Systems

    Article • January 2015, EDAA

    Dr Daniel Mueller-Gritschneder

  27. Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip

    Article • January 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  28. System C-based multi-level error injection for the evaluation of fault-tolerant systems

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  29. Fault-tolerant embedded control systems for unreliable hardware

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  30. Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  31. Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

    Article • Microelectronics Reliability, June 2014, Elsevier

    Dr Daniel Mueller-Gritschneder

  32. Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling

    Article • October 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  33. A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

    Article • IEEE Micro, July 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  34. A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs

    Article • April 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  35. Application of Dempster-Shafer Theory to task mapping under epistemic uncertainty

    Article • April 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  36. A Spectral Clustering Approach to Application-Specific Network-on-Chip Synthesis

    Article • January 2013, EDAA

    Dr Daniel Mueller-Gritschneder

  37. A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot

    Article • January 2013, EDAA

    Dr Daniel Mueller-Gritschneder

  38. Fast Cache Simulation for Host-Compiled Simulation of Embedded Software

    Article • January 2013, EDAA

    Dr Daniel Mueller-Gritschneder

  39. Analytical Timing Estimation for Temporally Decoupled TLMs Considering Resource Conflicts

    Article • January 2013, EDAA

    Dr Daniel Mueller-Gritschneder

  40. Hierarchical control flow matching for source-level simulation of embedded software

    Article • October 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  41. Automated construction of a cycle-approximate transaction level model of a memory controller

    Article • March 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  42. Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level

    Article • August 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  43. Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation

    Article • July 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  44. Computation of yield-optimized Pareto fronts for analog integrated circuit specifications

    Article • March 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Daniel Mueller-Gritschneder

  45. Pareto optimization of analog circuits considering variability

    Article • International Journal of Circuit Theory and Applications, March 2009, Wiley

    Dr Daniel Mueller-Gritschneder

  46. A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems

    Article • SIAM Journal on Optimization, January 2009, Society for Industrial & Applied Mathematics (SIAM)

    Dr Daniel Mueller-Gritschneder