All Stories

  1. MLonMCU: TinyML Benchmarking with Fast Retargeting
  2. Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM's UMA
  3. vRTLmod
  4. CompaSeC
  5. An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors
  6. REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance
  7. Automated HW/SW co-design for edge AI
  8. A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs
  9. Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs
  10. Analysis of Losses in Modular Reconfigurable Energy Storage Systems by SystemC TLM / AMS
  11. Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCs
  12. Supporting Design of Embedded Software that is robust against Hardware Errors.
  13. Model-based framework for networks-on-chip design space exploration
  14. Host-Compiled Simulation
  15. The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping
  16. Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models
  17. Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing
  18. Host-Compiled Simulation
  19. Embedded software reliability testing by unit-level fault injection
  20. Automation of FPGA performance monitoring and debugging Using IP-XACT and graph-grammars
  21. GRIP
  22. Application-aware cross-layer reliability analysis and optimization
  23. The Next Generation of Virtual Prototyping: Ultra-Fast Yet Accurate Simulation of HW/SW Systems
  24. Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip
  25. System C-based multi-level error injection for the evaluation of fault-tolerant systems
  26. Fault-tolerant embedded control systems for unreliable hardware
  27. Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies
  28. Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience
  29. Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling
  30. A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience
  31. A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs
  32. Application of Dempster-Shafer Theory to task mapping under epistemic uncertainty
  33. A Spectral Clustering Approach to Application-Specific Network-on-Chip Synthesis
  34. A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot
  35. Fast Cache Simulation for Host-Compiled Simulation of Embedded Software
  36. Analytical Timing Estimation for Temporally Decoupled TLMs Considering Resource Conflicts
  37. Hierarchical control flow matching for source-level simulation of embedded software
  38. Automated construction of a cycle-approximate transaction level model of a memory controller
  39. Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level
  40. Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation
  41. Computation of yield-optimized Pareto fronts for analog integrated circuit specifications
  42. Pareto optimization of analog circuits considering variability
  43. A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems