All Stories

  1. muRISCV-NN: Challenging Zve32x Autovectorization with TinyML Inference Library for RISC-V Vector Extension
  2. MLonMCU: TinyML Benchmarking with Fast Retargeting
  3. Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM's UMA
  4. vRTLmod
  5. CompaSeC
  6. An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors
  7. REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance
  8. Automated HW/SW co-design for edge AI
  9. A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs
  10. Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs
  11. Analysis of Losses in Modular Reconfigurable Energy Storage Systems by SystemC TLM / AMS
  12. Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCs
  13. Supporting Design of Embedded Software that is robust against Hardware Errors.
  14. Model-based framework for networks-on-chip design space exploration
  15. Host-Compiled Simulation
  16. The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping
  17. Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models
  18. Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing
  19. Host-Compiled Simulation
  20. Embedded software reliability testing by unit-level fault injection
  21. Automation of FPGA performance monitoring and debugging Using IP-XACT and graph-grammars
  22. GRIP
  23. Application-aware cross-layer reliability analysis and optimization
  24. The Next Generation of Virtual Prototyping: Ultra-Fast Yet Accurate Simulation of HW/SW Systems
  25. Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip
  26. System C-based multi-level error injection for the evaluation of fault-tolerant systems
  27. Fault-tolerant embedded control systems for unreliable hardware
  28. Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies
  29. Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience
  30. Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling
  31. A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience
  32. A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs
  33. Application of Dempster-Shafer Theory to task mapping under epistemic uncertainty
  34. A Spectral Clustering Approach to Application-Specific Network-on-Chip Synthesis
  35. A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot
  36. Fast Cache Simulation for Host-Compiled Simulation of Embedded Software
  37. Analytical Timing Estimation for Temporally Decoupled TLMs Considering Resource Conflicts
  38. Hierarchical control flow matching for source-level simulation of embedded software
  39. Automated construction of a cycle-approximate transaction level model of a memory controller
  40. Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level
  41. Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation
  42. Computation of yield-optimized Pareto fronts for analog integrated circuit specifications
  43. Pareto optimization of analog circuits considering variability
  44. A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems