All Stories

  1. A 300-GHz-Band 36-Gb/s Scalable 2-D Phased-Array CMOS Double Superheterodyne Receiver
  2. Calibration method for complex permittivity measurements using s-SNOM combining multiple probe tapping harmonics
  3. Formulating microwave measurement and design in terms of X-parameters using signal flow graphs
  4. A 76-Gbit/s 265-GHz CMOS Receiver With WR-3.4 Waveguide Interface
  5. 300-GHz-Band OFDM Video Transmission with CMOS TX/RX Modules and 40dBi Cassegrain Antenna toward 6G
  6. Variable-Temperature Noise Characterization of N-MOSFETs Using an In-Situ Broadband Amplifier
  7. A 258-GHz CMOS Transmitter with Phase-Shifting Architecture for Phased-Array Systems
  8. A 32-Gb/s CMOS Receiver With Analog Carrier Recovery and Synchronous QPSK Demodulation
  9. Direct White Noise Characterization of Short-Channel MOSFETs
  10. Direct white noise characterization of short-channel MOSFETs
  11. Session 23 Overview: THz Circuits and Front-Ends
  12. White Noise Characterization of N-MOSFETs for Physics-Based Cryogenic Device Modeling
  13. Variable-Temperature Noise Characterization of N-MOSFETs Using an In-Situ Broadband Amplifier
  14. An 80-Gb/s 300-GHz-Band Single-Chip CMOS Transceiver
  15. A 6-mW-DC-Power 300-GHz CMOS Receiver for Near-Field Wireless Communications
  16. A −40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency
  17. Highly Configurable Cylindrical-Resonator-Based Bandpass Filter Built of Silica-Based Post-Wall Waveguide and Its Application to Compact E-Band Hybrid-Coupled Diplexer
  18. Wideband Power-Line Decoupling Technique for Millimeter-Wave CMOS Integrated Circuits
  19. 9.5 An 80Gb/s 300GHz-Band Single-Chip CMOS Transceiver
  20. Causal Characteristic Impedance Determination Using Calibration Comparison and Propagation Constant
  21. 300-GHz CMOS Transceiver for Terahertz Wireless Communication
  22. 32-Gbit/s CMOS Receivers in 300-GHz Band
  23. 300-GHz CMOS transmitter module with built-in waveguide transition on a multilayered glass epoxy PCB
  24. A 40 dB peak gain, wideband, low noise intermediate frequency (IF) amplifier
  25. An E-band hybrid-coupled diplexer built of silica-based post-wall waveguide
  26. A 416-mW 32-Gbit/s 300-GHz CMOS receiver
  27. 56-Gbit/s 16-QAM wireless link with 300-GHz-band CMOS transmitter
  28. A 32Gbit/s 16QAM CMOS receiver in 300GHz band
  29. An 80–106 GHz CMOS amplifier with 0.5V supply voltage
  30. Causal transmission line model incorporating frequency-dependent linear resistors
  31. DC and RF characterization of RF MOSFET embedding structure
  32. 17.9 A 105Gb/s 300GHz CMOS transmitter
  33. Integrated-Circuit Approaches to THz Communications: Challenges, Advances, and Future Prospects
  34. A 300 GHz CMOS Transmitter With 32-QAM 17.5 Gb/s/ch Capability Over Six Channels
  35. Characterization of 60-GHz silica-based post-wall waveguide and low-loss substrate dielectric
  36. A 300-GHz 64-QAM CMOS transmitter with 21-Gb/s maximum per-channel data rate
  37. Power spectrum analysis of a tripler-based 300-GHz CMOS up-conversion mixer
  38. 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique
  39. System-level evaluation of 300GHz CMOS wireless transmitter using cubic mixer
  40. Terahertz CMOS transmitter supporting high-order digital modulation
  41. CMOS 300-GHz 64-QAM transmitter
  42. Quintic mixer: A subharmonic up-conversion mixer for THz transmitter supporting complex digital modulation
  43. Compact 141-GHz Differential Amplifier with 20-dB Peak Gain and 22-GHz 3-dB Bandwidth
  44. Scattered Reflections on Scattering Parameters — Demystifying Complex-Referenced S Parameters —
  45. 20.1 A 300GHz 40nm CMOS transmitter with 32-QAM 17.5Gb/s/ch capability over 6 channels
  46. 124-GHz CMOS quadrature voltage-controlled oscillator with fundamental injection locking
  47. Calibration of process parameters for electromagnetic field analysis of CMOS devices up to 330 GHz
  48. Compact 138-GHz amplifier with 18-dB peak gain and 27-GHz 3-dB bandwidth
  49. Comparative analysis of on-chip transmission line de-embedding techniques
  50. Modeling of wideband decoupling power line for millimeter-wave CMOS circuits
  51. Parasitic conscious 54 GHz divide-by-4 injection-locked frequency divider
  52. 300-GHz MOSFET model extracted by an accurate cold-bias de-embedding technique
  53. Compact 160-GHz amplifier with 15-dB peak gain and 41-GHz 3-dB bandwidth
  54. Compact and low-loss bandpass filter realized in silica-based post-wall waveguide for 60-GHz applications
  55. Wideband CMOS decoupling power line for millimeter-wave applications
  56. Characterization of wideband decoupling power line with extremely low characteristic impedance for millimeter-wave CMOS circuits
  57. Systematic calibration procedure of process parameters for electromagnetic field analysis of millimeter-wave CMOS devices
  58. Tehrahertz CMOS Design for Low-Power and High-Speed Wireless Communication
  59. Recent progress and prospects of terahertz CMOS
  60. 79GHz CMOS power amplifier using temperature compensation bias
  61. Design of CMOS resonating push-push frequency doubler
  62. Design of millimeter-wave CMOS transmission-line-to-waveguide transitions
  63. Evaluation of CMOS differential transmission lines as two-port networks with on-chip baluns in millimeter-wave band
  64. Design of well-behaved low-loss millimetre-wave CMOS transmission lines
  65. Process parameter calibration for millimeter-wave CMOS back-end device design with electromagnetic field analysis
  66. E-Band 65nm CMOS Low-Noise Amplifier Design Using Gain-Boost Technique
  67. CMOS power amplifier with temperature compensation for 79 GHz radar system
  68. Evaluation of temperature dependence and lifetime of 79GHz power amplifier
  69. An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS
  70. On the length of THRU standard for TRL de-embedding on Si substrate above 110 GHz
  71. Modeling of Short-Millimeter-Wave CMOS Transmission Line with Lossy Dielectrics with Specific Absorption Spectrum
  72. On the choice of cascade de-embedding methods for on-wafer S-parameter measurement
  73. Characteristic impedance determination technique for CMOS on-wafer transmission line with large substrate loss
  74. 1.2–17.6 GHz Ring-Oscillator-Based Phase-Locked Loop with Injection Locking in 65 nm Complementary Metal Oxide Semiconductor
  75. RF signal generator using time domain harmonic suppression technique in 90nm CMOS
  76. A Study of Digitally Controllable Radio Frequency Micro Electro Mechanical Systems Inductor
  77. 2.4–10 GHz Low-Noise Injection-Locked Ring Voltage Controlled Oscillator in 90 nm Complementary Metal Oxide Semiconductor
  78. Modeling of Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor for Accurate Prediction of Junction Condition on Device Characteristics
  79. Universal Relationship between Substrate Current and History Effect in Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors
  80. Interconnect Design Challenges in Nano CMOS Circuit
  81. RF CMOS Integrated Circuit: History, Current Status and Future Prospects
  82. High-Frequency Transmission Characteristics of the Interconnects Stacked into the 3D IC Configuration
  83. HiSIM-SOI: Complete surface-potential-based model valid for all SOI-structure types
  84. Inductorless 8.9 mW 25 Gb/s 1:4 DEMUX and 4 mW 13 Gb/s 4:1 MUX in 90 nm CMOS
  85. Radio Frequency Micro Electro Mechanical Systems Inductor Configurations for Achieving Large Inductance Variations and High Q-factors
  86. Low-phase-noise wide-frequency-range ring-VCO-based scalable PLL with subharmonic injection locking in 0.18 µm CMOS
  87. Design of On-Chip High Speed Interconnect on Complementary Metal Oxide Semiconductor 180 nm Technology
  88. RF Signal Generator Based on Time-to-Analog Converter in 0.18 µm Complementary Metal Oxide Semiconductor
  89. A Thru-Only De-Embedding Method Foron-Wafer Characterization of Multiport Networks
  90. On the validity of bisection-based thru-only de-embedding
  91. Wide-band, high linear low noise amplifier design in 0.18um CMOS technology
  92. A Universal Equivalent Circuit Model for Ceramic Capacitors
  93. Highly Energy-Efficient On-Chip Pulsed-Current-Mode Transmission Line Interconnect
  94. Design of CMOS inverter-based output buffers adapting the cherry-hooper broadbanding technique
  95. SMAFTI packaging technology for new interconnect hierarchy
  96. S-Parameter-Based Modal Decomposition of Multiconductor Transmission Lines and Its Application to De-Embedding
  97. A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process
  98. Physical design challenges to nano-CMOS circuits
  99. An 8.9mW 25Gb/s inductorless 1:4 DEMUX in 90nm CMOS
  100. Inter-Chip Wiring Technology for 3-D LSI
  101. Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress
  102. Single-parameter nonadiabatic quantized charge pumping
  103. Adaptable wire-length distribution with tunable occupation probability
  104. A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation
  105. Nanosilicon for single-electron devices
  106. Cross-coupling in Coulomb blockade circuits: Bidirectional electron pump
  107. A New Approach to Failure Analysis and Yield Enhancement of Very Large-scale Integrated Systems
  108. Characteristics of two Coulomb blockade transistors separated by an island to which an oscillating potential is applied: Theory and experiment
  109. Nanoscale Coulomb blockade memory and logic devices
  110. Analysis of multiphase clocked electron pumps consisting of single-electron transistors
  111. Charging and Retention Times in Silicon-Floating-Dot-Single-Electron Memory
  112. Scaling of the single-electron tunnelling current through ultrasmall tunnel junctions
  113. A Simple Model of a Single-Electron Floating Dot Memory for Circuit Simulation
  114. Circuit Simulators Aiming at Single-Electron Integration
  115. Correlated Electron-Hole Transport in Capacitively-Coupled One-Dimensional Tunnel Junction Arrays
  116. Estimation of Cotunneling in Single-Electron Logic and Its Suppression