All Stories

  1. Computational Analysis of the Effects of Nanoscale Confinement on the Structure of Low-k Dielectric Hybrid Organosilicate Materials

    Article • IEEE Transactions on Materials for Electron Devices, January 2024, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  2. Florets for Chiplets for running Datacenter scale CNNs concurrently

    Article • ACM Transactions on Embedded Computing Systems, September 2023, ACM (Association for Computing Machinery)

    Harsh Sharma, Dr. Rasit O Topaloglu

  3. Quantum Logic Locking for Security

    Article • J — Multidisciplinary Scientific Journal, July 2023, MDPI AG

    Dr. Rasit O Topaloglu

  4. SCANN: Side Channel Analysis of Spiking Neural Networks

    Article • Cryptography, March 2023, MDPI AG

    Dr. Rasit O Topaloglu

  5. Quantum Machine Learning for Ocular Disease Recognition

    Article • March 2023, MDPI AG

    Dr. Rasit O Topaloglu

  6. ObfusX: Routing obfuscation with explanatory analysis of a machine learning attack

    Article • Integration, March 2023, Elsevier

    Dr. Rasit O Topaloglu

  7. Exploring Topological Semi-Metals for Interconnects

    Article • Journal of Low Power Electronics and Applications, February 2023, MDPI AG

    Dr. Rasit O Topaloglu

  8. When a Quantum Scientist Interviews ChatGPT

    Article • February 2023, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  9. Quantum Logic Locking for Security

    Article • December 2022, MDPI AG

    Dr. Rasit O Topaloglu

  10. Quantum Machine Learning for Material Synthesis and Hardware Security (Invited Paper)

    Article • October 2022, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  11. Optimization of Quantum Read-Only Memory Circuits

    Article • October 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  12. A Shuttle-Efficient Qubit Mapper for Trapped-Ion Quantum Computers

    Article • June 2022, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  13. Muzzle the Shuttle: Efficient Compilation for Multi-Trap Trapped-Ion Quantum Computers

    Article • March 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  14. Shuttle-Exploiting Attacks and Their Defenses in Trapped-Ion Quantum Computers

    Article • IEEE Access, January 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  15. Quantum-Classical Hybrid Machine Learning for Image Classification (ICCAD Special Session Paper)

    Article • November 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  16. Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach

    Article • November 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  17. Split Compilation for Security of Quantum Circuits

    Article • November 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  18. Lorax: Machine Learning-Based Oracle Reconstruction With Minimal I/O Patterns

    Article • July 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  19. Quantum PUF for Security and Trust in Quantum Computing

    Article • IEEE Journal on Emerging and Selected Topics in Circuits and Systems, June 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  20. A Survey and Tutorial on Security and Resilience of Quantum Computing

    Article • May 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  21. Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization

    Article • February 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Cristina Meinhardt, Dr. Rasit O Topaloglu

  22. ObfusX

    Article • January 2021, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  23. Quantum Generative Models for Small Molecule Drug Discovery

    Article • IEEE Transactions on Quantum Engineering, January 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  24. Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer

    Article • March 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  25. Beyond-CMOS Technologies for Next Generation Computer Design

    Article • January 2019, Springer Science + Business Media

    Dr. Rasit O Topaloglu

  26. Editorial for TODAES Special Issue on Internet of Things System Performance, Reliability, and Security

    Article • ACM Transactions on Design Automation of Electronic Systems, November 2018, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  27. MapReduce-based pattern classification for design space analysis

    Article • April 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  28. Editorial for JETC Special Issue on Alternative Computing Systems

    Article • ACM Journal on Emerging Technologies in Computing Systems, May 2017, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  29. Identification and sensitivity analysis of a correlated ground rule system (design arc)

    Article • April 2017, SPIE

    Dr. Rasit O Topaloglu

  30. ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite

    Article • November 2016, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  31. E-beam inspection throughput acceleration via Targeted Critical Area Inspection

    Article • May 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  32. More than Moore Technologies for Next Generation Computer Design

    Article • January 2015, Springer Science + Business Media

    Dr. Rasit O Topaloglu

  33. Design and technology co-optimization near single-digit nodes

    Article • November 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  34. ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite

    Article • November 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  35. Guest Editorial: Special Section on Optical Interconnects

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  36. Design with FinFETs: Design rules, patterns, and variability

    Article • November 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  37. Chip-scale physical interconnect models (Tutorial)

    Article • June 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  38. Welcome to ISQED 2013

    Article • March 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  39. Guest Editors' Introduction to Practical Parallel EDA

    Article • IEEE Design and Test, February 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  40. Efficient multi-die placement for blank defect mitigation in EUV lithography

    Article • March 2012, SPIE

    Dr. Rasit O Topaloglu

  41. Recent Topics on Modeling of Semiconductor Processes, Devices and Circuits

    Article • March 2012, Bentham Science Publishers

    Dr. Rasit O Topaloglu

  42. Characterization and decomposition of self-aligned quadruple patterning friendly layout

    Article • February 2012, SPIE

    Dr. Rasit O Topaloglu

  43. Block-level 3D IC design with through-silicon-via planning

    Article • January 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  44. TSV density-driven global placement for 3D stacked ICs

    Article • November 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  45. GPU programming for EDA with OpenCL

    Article • November 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  46. Hot spot detection for indecomposable self-aligned double patterning layout

    Article • October 2011, SPIE

    Dr. Rasit O Topaloglu

  47. EUV mask preparation considering blank defects mitigation

    Article • October 2011, SPIE

    Dr. Rasit O Topaloglu

  48. Effective decomposition algorithm for self-aligned double patterning lithography

    Article • March 2011, SPIE

    Dr. Rasit O Topaloglu

  49. Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs

    Article • March 2011, SPIE

    Dr. Rasit O Topaloglu

  50. Is manufacturability with double patterning a burden on designer? Analyses of device and circuit aspects

    Article • March 2011, SPIE

    Dr. Rasit O Topaloglu

  51. Device and circuit implications of double-patterning — A designer's perspective

    Article • March 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  52. Fast variational static IR-drop analysis on the graphical processing unit

    Article • March 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  53. Self-aligned double patterning decomposition for overlay minimization and hot spot detection

    Article • January 2011, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  54. Applications driving 3D integration and corresponding manufacturing challenges

    Article • January 2011, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  55. Test structures to quantify contact placement-impacted drain current variations

    Article • March 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  56. SIS wide-band model extraction methodology for SOI on-chip inductor

    Article • March 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  57. Assessing chip-level impact of double patterning lithography

    Article • March 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  58. 3-2-1 contact

    Article • January 2010, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  59. Is overlay error more important than interconnect variations in double patterning?

    Article • July 2009, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  60. CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design

    Article • March 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  61. Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  62. Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics

    Article • March 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  63. DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances

    Article • IEEE Transactions on Semiconductor Manufacturing, January 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  64. Exploiting STI stress for performance

    Article • November 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  65. A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances

    Article • March 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  66. Energy-Minimization Model for Fill Synthesis

    Article • March 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  67. Process Variation-Aware Multiple-Fault Diagnosis of Thermometer-Coded Current-Steering DACs

    Article • IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing, February 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  68. Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization

    Article • January 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  69. Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction

    Article • October 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  70. Novel multiple function analog filter structures and a dual-mode multifunction filter

    Article • International Journal of Electronics, September 2006, Taylor & Francis

    Dr. Rasit O Topaloglu

  71. Generation of design guarantees for interconnect matching

    Article • March 2006, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  72. Statistical Compact Modeling and Si Verification Methodology

    Article • January 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  73. A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs

    Article • January 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  74. Forward discrete probability propagation method for device performance characterization under process variations

    Article • January 2005, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  75. New current–mode special function continuous-time active filters employing only OTAs and OPAMPs

    Article • International Journal of Electronics, June 2004, Taylor & Francis

    Dr. Rasit O Topaloglu

  76. Current-input Current-output Notch and Bandpass Analog Filter Structures as Alternatives to Active-R Circuits

    Article • Frequenz, January 2003, De Gruyter

    Dr. Rasit O Topaloglu

  77. Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  78. High-Performance Computing for Theoretical Study of Nanoscale and Molecular Interconnects

    Article • IGI Global

    Dr. Rasit O Topaloglu

  79. Monte Carlo-Alternative Probabilistic Simulations for Analog Systems

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  80. On mismatch in the deep sub-micron era-from physics to circuits

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu