All Stories

  1. Guest Editors' Introduction to Practical Parallel EDA

    Article • IEEE Design and Test, February 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  2. Efficient multi-die placement for blank defect mitigation in EUV lithography

    Article • March 2012, SPIE

    Dr. Rasit O Topaloglu

  3. Recent Topics on Modeling of Semiconductor Processes, Devices and Circuits

    Article • March 2012, Bentham Science Publishers

    Dr. Rasit O Topaloglu

  4. Characterization and decomposition of self-aligned quadruple patterning friendly layout

    Article • February 2012, SPIE

    Dr. Rasit O Topaloglu

  5. Block-level 3D IC design with through-silicon-via planning

    Article • January 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  6. TSV density-driven global placement for 3D stacked ICs

    Article • November 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  7. Hot spot detection for indecomposable self-aligned double patterning layout

    Article • October 2011, SPIE

    Dr. Rasit O Topaloglu

  8. EUV mask preparation considering blank defects mitigation

    Article • October 2011, SPIE

    Dr. Rasit O Topaloglu

  9. Effective decomposition algorithm for self-aligned double patterning lithography

    Article • March 2011, SPIE

    Dr. Rasit O Topaloglu

  10. Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs

    Article • March 2011, SPIE

    Dr. Rasit O Topaloglu

  11. Is manufacturability with double patterning a burden on designer? Analyses of device and circuit aspects

    Article • March 2011, SPIE

    Dr. Rasit O Topaloglu

  12. Self-aligned double patterning decomposition for overlay minimization and hot spot detection

    Article • January 2011, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  13. Applications driving 3D integration and corresponding manufacturing challenges

    Article • January 2011, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  14. Test structures to quantify contact placement-impacted drain current variations

    Article • March 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  15. SIS wide-band model extraction methodology for SOI on-chip inductor

    Article • March 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  16. Assessing chip-level impact of double patterning lithography

    Article • March 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  17. 3-2-1 contact

    Article • January 2010, ACM (Association for Computing Machinery)

    Dr. Rasit O Topaloglu

  18. CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design

    Article • March 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  19. Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  20. DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances

    Article • IEEE Transactions on Semiconductor Manufacturing, January 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  21. Exploiting STI stress for performance

    Article • November 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  22. Process Variation-Aware Multiple-Fault Diagnosis of Thermometer-Coded Current-Steering DACs

    Article • IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing, February 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  23. Novel multiple function analog filter structures and a dual-mode multifunction filter

    Article • International Journal of Electronics, September 2006, Taylor & Francis

    Dr. Rasit O Topaloglu

  24. Statistical Compact Modeling and Si Verification Methodology

    Article • January 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  25. New current–mode special function continuous-time active filters employing only OTAs and OPAMPs

    Article • International Journal of Electronics, June 2004, Taylor & Francis

    Dr. Rasit O Topaloglu

  26. Current-input Current-output Notch and Bandpass Analog Filter Structures as Alternatives to Active-R Circuits

    Article • Frequenz, January 2003, De Gruyter

    Dr. Rasit O Topaloglu

  27. Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Dr. Rasit O Topaloglu

  28. High-Performance Computing for Theoretical Study of Nanoscale and Molecular Interconnects

    Article • IGI Global

    Dr. Rasit O Topaloglu