All Stories

  1. CeConP: Exploring Node Centrality for Early Routing Congestion Prediction
  2. Fast and Low-Error Prediction of Logic Gate Cell Characterization
  3. New Modified 4:2 Approximate Compressors for Low-Power Applications
  4. A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures
  5. Impact on Radiation Robustness of Gate Mapping in FinFET Circuits under Work-function Fluctuation
  6. Adaptive Batch Size CGP: Improving Accuracy and Runtime for CGP Logic Optimization Flow
  7. Review of Machine Learning in Logic Synthesis
  8. Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology
  9. Optimizing machine learning logic circuits with constant signal propagation
  10. E-RVP: An Initial Design Rule Violation Predictor Using Placement Information
  11. Approximation Workflow for Energy-Efficient Comparators in Decision Tree Applications
  12. Exploring Approximate Comparator Circuits on Power Efficient Design of Decision Trees
  13. Exploring Approximate Computing Approaches to Design Power-efficient Multipliers
  14. Routability-Driven Detailed Placement Using Reinforcement Learning
  15. Exploring Machine Learning for Electrical Behavior Prediction: The CMOS Inverter Case Study
  16. Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing
  17. A Decision Tree Synthesis Flow for Precise and Approximate Circuits
  18. CGP-based Logic Flow: Optimizing Accuracy and Size of Approximate Circuits
  19. An architecture proposal for checkpoint/restore on stateful containers
  20. Accuracy-Configurable 2-D Gaussian Filter Architecture for Energy-Efficient Image Processing
  21. Exploring the Impacts of Multiple Kernel Sizes of Gaussian Filters Combined to Approximate Computing in Canny Edge Detection
  22. Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study
  23. SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology
  24. Accuracy and Size Trade-off of a Cartesian Genetic Programming Flow for Logic Optimization
  25. Exploring Approximate Computing and Near- Threshold Operation to Design Energy -efficient Multipliers
  26. Exploring Constant Signal Propagation to Optimize Neural Network Circuits
  27. A Multi-Agent-Based Network-on-Chip Simulator
  28. FinFET Inverter Designs: Behavior and Challenges of Process Variability
  29. Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders
  30. Fast Logic Optimization Using Decision Trees
  31. Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions
  32. Current Behavior on Process Variability Aware FinFET Inverter Designs
  33. Soft Error Sensibility Window at FinFET DICE SRAM
  34. Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit
  35. Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization
  36. EDAS2020: IEEE CASS/CEDA Seasonal School on Electronic Design Automation [CAS Society News]
  37. Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs
  38. Energy-Efficient Design of Approximated Full Adders
  39. Mirror Full Adder SET Susceptibility on 7nm FinFET Technology
  40. Circuit design using Schmitt Trigger to reliability improvement
  41. Soft Error Impact on FinFET and CMOS XOR Logic Gates
  42. A Fine-grained Methodology for Accuracy-configurable and Energy-efficient Gaussian Filters Design
  43. Mitigation Effects of Decoupling Cells on Full Adders Process Variability
  44. Circuit Level Design Methods to Mitigate Soft Errors
  45. Soft Error Reliability of SRAM cells during the three operation states
  46. Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters
  47. Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology
  48. Process Variability Impact on the SET Response of FinFET Multi-level Design
  49. Robust FinFET Schmitt Trigger Designs for Low Power Applications
  50. FBM: A Simple and Fast Algorithm for Placement Legalization
  51. FinFET Variability and Near-threshold operation: Impact on Full Adders design using XOR Blocks
  52. Radiation Effects in XOR Logic Gates at 16nm CMOS and FinFET Technology
  53. Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility
  54. Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs
  55. Evaluation of SET under Process Variability on FinFET Multi-level Design
  56. Impact of Process Variability and Single Event Transient on FinFET Technology
  57. Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability
  58. Robustness and Minimum Energy-Oriented FinFET Design
  59. Circuit-Level Hardening Techniques to Mitigate Soft Errors in FinFET Logic Gates
  60. Gate mapping impact on variability robustness in FinFET technology
  61. Mitigation of process variability effects using decoupling cells
  62. Exploring Schmitt Trigger Circuits for Process Variability Mitigation
  63. A library for services transparent replication
  64. Process Variability Challenges for Radiation Mitigation Techniques on 16nm
  65. Exploring MAS to a High Level Abstration NoC Simulation Environment
  66. Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells
  67. Impact of Near-Threshold and Variability on 7nm FinFET XOR Circuits
  68. Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements
  69. Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies
  70. Evaluation of variability using Schmitt trigger on full adders layout
  71. Impact of different transistor arrangements on gate variability
  72. 16NM 6T and 8T CMOS SRAM Cell Robustness Against Process Variability and Aging Effects
  73. Pros and Cons of Schmitt Trigger Inverters to Mitigate PVT Variability on Full Adders
  74. Reliability evaluation of circuits designed in multi- and single-stage versions
  75. Comparing 32nm full adder TMR and DTMR architectures
  76. Impact of schmitt trigger inverters on process variability robustness of 1-Bit full adders
  77. SET response of FinFET-based majority voter circuits under work-function fluctuation
  78. Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices
  79. Implications of Work-Function Fluctuation on Radiation Robustness of FinFET XOR Circuits
  80. Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition
  81. Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology
  82. Robustness of Sub-22nm multigate devices against physical variability
  83. Radiation sensitivity of XOR topologies in multigate technologies under voltage variability
  84. Robustness evaluation of finFET transistors under PVT variability
  85. Geometric variability impact on 7nm Trigate combinational cells
  86. PVT variability analysis of FinFET and CMOS XOR circuits at 16nm
  87. Permanent and single event transient faults reliability evaluation EDA tool
  88. Investigating PVT variability effects on full adders
  89. Inserting permanent fault input dependence on PTM to improve robustness evaluation
  90. FinFET cells with different transistor sizing techniques against PVT variations
  91. A probabilistic model for stuck-on faults in combinational logic gates
  92. Reliability analysis of majority voters under permanent faults
  93. An evaluation of BTI degradation of 32nm standard cells
  94. Process variability in FinFET standard cells with different transistor sizing techniques
  95. Impact of PVT variability on 20 nm FinFET standard cells
  96. Impact of gate workfunction fluctuation on FinFET standard cells
  97. Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices
  98. Predictive evaluation of electrical characteristics of sub-22nm FinFET technologies under device geometry variations
  99. Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices
  100. Comparing high-performance cells in CMOS bulk and FinFET technologies
  101. Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs
  102. A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage
  103. A yield-driven regular layout synthesis
  104. FinFET basic cells evaluation for regular layouts
  105. Evaluation of process variability on current for nanotechnologies devices
  106. A Low-Cost Solution for Deploying Processor Cores in Harsh Environments
  107. An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs
  108. Recovery scheme for hardening system on programmable chips
  109. Logic and Physical Synthesis of Cell Arrays
  110. orBDDs Direct Mapping for Structured Logic Circuits
  111. Design of Regular Layouts to Improve Predictability
  112. A Regular Layout Approach for ASICs