All Stories

  1. Improved optical performance of a photo-gated tunnel FET with hetero-dielectric and PNPN configuration
  2. TCAD-based optical FoM analysis of doping-less TFET photosensors with geometrically engineered channels for near-infrared (NIR) light detection
  3. Enhanced optical performance of a dual-drain vertical TFET photosensor for near-infrared light detection
  4. High-sensitivity detection in biosensors: A comparative study of inverted T- and L-channel charge plasma TFETs
  5. Comprehensive Analysis on Complementary FET
  6. Impact of Dielectric Materials in an Asymmetrical Shaped Band to Band TFET
  7. TFET Based Biosensor Using Dielectric Modulation Technique
  8. Negative capacitance split source tunnel FET as dielectric modulated highly sensitive biosensor
  9. Performance Analysis of Double-Gate Junctionless Tunnel FET with a Stepped Channel
  10. Performance Investigation of L-Shaped Extended Source TFET-Based Photosensor for Near-Infrared Light Sensing Applications
  11. Design and Simulation of A Dielectric-Modulated TFET based Biosensor Using Extended Source Configuration
  12. Interfacial charge and temperature analysis of gate-all-around line tunneling TFET for improved device reliability
  13. Performance analysis of highly sensitive vertical tunnel FET for detecting light in near-IR range
  14. A dielectrically modulated vertical TFET-based biosensor considering irregular probe placement and steric hindrance issues
  15. Performance investigation of ferroelectric L-shaped tunnel FET with suppressed corner tunneling for low power applications
  16. Self-cascode and self-biased Dickson charge pump for fast locking wide lock range PLL with reduced phase noise
  17. Reduced OFF-state current and suppressed ambipolarity in a dopingless vertical TFET with dual-drain for high-frequency circuit applications
  18. Performance investigation of elevated source EBG TFET based photosensor for near-infrared light sensing applications
  19. Demonstration of a novel Dual-Source Elevated-Channel Dopingless TFET with improved DC and Analog/RF performance
  20. Physics based model development of a double gate reverse T-shaped channel TFET including 1D and 2D band-to-band tunneling components
  21. Physics based analysis of a High-Performance Dual line Tunneling TFET with Reduced Corner Effects
  22. Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET
  23. Radiation Effects and Their Impact on SRAM Design
  24. Final Summary and Future of Advanced Ultra Low Power Metal Oxide Semiconductor Field Effect Transistors
  25. Mathematical Approach for a Future Semiconductor Roadmap
  26. Mathematical Approach for the Foundation of Negative Capacitance Technology
  27. GaSb/GaAs Type‐II heterojunction GAA‐TFET with core source for enhanced analog/RF performance and reliability
  28. Reduction of Corner Effect in ZG-ES-TFET for Improved Electrical Performance and its Reliability Analysis in the Presence of Traps
  29. Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET
  30. A Review on Emerging Tunnel FET Structures for High-speed and Low-power Circuit Applications
  31. DC Analysis and Analog/HF Performances of GAA-TFET with Dielectric Pocket
  32. TFET-based Memory Cell Design with Top-Down Approach
  33. Performance Investigation of a Vertical TFET with Inverted-T Channel for Improved DC and Analog/Radio-Frequency Parameters
  34. Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic
  35. Demonstration of L-Channel Tunnel FET with Triple Metal Gate for Next Generation IC Technology
  36. Extended Source Tunnel Field-Effect Transistor with Source Pocket Integration
  37. A Dual-Drain Vertical Tunnel FET with Improved Device Performance: Proposal, Optimization, and Investigation
  38. A Novel Extended Back-Gate Negative Capacitance TFET for Improved Device Performance
  39. Drain Engineered Charge Plasma-based Vertical TFET for Improved Device Performance
  40. Investigation of Novel Z-shaped Gate TFET with Improved Device Characteristics
  41. Source Extended GaSb/GaAs Heterojunction GAATFET to Improve ION/IOFF Ratio
  42. Design and Investigation of a Novel Gate-All-Around Vertical Tunnel FET with Improved DC and Analog/RF Parameters
  43. Improved DC Performance of Nanotube Junctionless Field-Effect Transistors with Dielectric Pocket Integration
  44. Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction
  45. A Review of Tunnel Field-Effect Transistors for Improved ON-State Behaviour
  46. Memory Designing Using Low-Power FETs for Future Technology Nodes
  47. Tunnel Field-Effect Transistor
  48. Dielectric Engineered Cylindrical Junctionless FET for Low Power Applications
  49. Dielectric Pocket Nanotube Junctionless Field-effect Transistor based Biosensor
  50. TCAD Analysis of Dielectric Pocket Nanowire Junctionless Field-Effect Transistor based Biosensor
  51. Theoretical investigation on un-doped and doped TiO2 for solar cell application
  52. A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET
  53. A Hetero-Dielectric Double-Gate Junctionless FET with Spacer for Improved Device Performances
  54. Enhanced DC Performance of Junctionless Field-effect Transistor Using Dielectric Engineering
  55. Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes
  56. Improved DC Performances of Gate-all-around Si-Nanotube Tunnel FETs Using Gate-Source Overlap
  57. Tuning of Threshold Voltage in Silicon Nano-Tube FET Using Halo doping and its Impact on Analog/RF Performances
  58. Determination of Structural, Electronic, Optical and Mechanical Properties of Brookite TiO2Using Various Exchange-Correlation
  59. Improvement in analog/RF performances of SOI TFET using dielectric pocket
  60. Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances
  61. Performance enhancement of double-gate tunnel FETs using dual-metal and graded-channel configuration
  62. Comparative analysis of silicon nano tube FET for switching applications using high K and work function modulation
  63. Design and analysis of High K Silicon Nano Tube Tunnel FET Device
  64. Structure, Stability and Electronic Properties of Thin TiO2 Nanowires of Different Novel Shapes: An Ab- initio Study
  65. Comparative Study of High K in Silicon Nano Tube FET for Switching Applications
  66. A Novel Structure of Double-Gate Tunnel FET with Extended Back Gate for Improved Device Performances
  67. Analysis of Interface Trap Charges on Dielectric Pocket SOI-TFET
  68. Structure and Electronic Properties of TiO2 Nanowires of Different Geometrical Shapes: An Abinitio Study
  69. Design and Analysis of High Performance Multiplier Circuit
  70. Structural, electronic, and mechanical properties of anatase titanium dioxide
  71. Effect of strain in silicon nanotube FET devices for low power applications
  72. Dual-Metal Graded-Channel Double-Gate Tunnel FETs for Reduction of Ambipolar Conduction
  73. A Novel Structure of Tunnel FET with Suppressed Ambipolar Conduction Using Dielectric Pocket
  74. DETERMINATION OF DIFFERENT OPTICAL PROPERTIES FOR CUBIC TITANIUM DIOXIDE: AN AB – INITIO APPROACH
  75. Impact of Dielectric Pocket on Analog and High-Frequency Performances of Cylindrical Gate-All-Around Tunnel FETs
  76. Structural, electronic, and mechanical properties of cubic TiO 2 : A first-principles study