A Novel Structure of Tunnel FET with Suppressed Ambipolar Conduction Using Dielectric Pocket

What is it about?

Impact of high-k dielectric pocket (DP) in drain region on ambipolar conduction of TFETs is demonstrated. It is demonstrated that due to enhancement of depleted drain region under DP, tunneling width at channel-drain interface increases, and a significant reduction in ambipolarity is achieved. It is shown that ON-state current, subthreshold swing and output characteristics are not affected with presence of proposed DP. The gate-to-drain capacitance is reduced with inclusion of DP, thus leading to improved cutoff frequency. It is also demonstrated that only 10-nm of gate-on-drain overlapping with DP can eliminate ambipolarity for higher gate voltage of -0.8 V.

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Why is it important?

First time a dielectric pocket has been used in SOI-TFET to remove ambipolarity.