What is it about?

This work provides a highly efficient iterative flow that searches for the best HLS directive configuration for a specific design, which produces the Verilog design with low latency (number of clock cycles) and high frequency under a floorplan constraint on multi-die FPGAs.

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Why is it important?

Difficulties are two-fold. 1. For directive search: (1.1) It is already faced with a large design space. For Example, the Vitis HLS 2020.2 has 26 directives, each having numerous possible parameter settings. (1.2) Besides, HLS directives and QoRs (latency, resource, etc.) have non-monotonic relationships, which requires the DSE algorithm to effectively avoid getting trapped in local optima. (1.3) Additionally, previous directive search works only consider the overall resource on an FPGA, i.e., only suitable for single-die FPGAs. 2. For floorplan: Floorplanning on multi-die FPGAs has been proven to be an effective way to maximize the achievable frequency. However, the previous SOTAs using MILP solver for finding an ideal floorplan is too time-consuming. Hence, we design a highly efficient iterative flow, integrating an incremental floorplan legalization with latency-bottleneck-guided directive search, to achieve orders-of-magnitude faster co-search than the previous SOTA, meanwhile achieving better QoR on both latency (cycles) and frequency (MHz).

Perspectives

Four years, from knowing FPGA for the first time, to the first publication on FPGA. From the very beginning of digital circuit design, to attempts on understanding [research], after three times of compromise or giving up on projects that had been carried out for half to a whole year, until now, I have just got started on electronic design automation (EDA). FADO was published and presented at the International Symposium on FPGA 2023. This is a work on co-optimization of Design Space Exploration (DSE) in High Level Synthesis (HLS) and Floorplanning in physical design to improve design performance on multi-die FPGAs. It is such a great honor to work with my kind, intelligent, conscientious and patient co-authors.

Linfeng Du
Hong Kong University of Science and Technology

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This page is a summary of: FADO: F loorplan- A ware D irective O ptimization for High-Level Synthesis Designs on Multi-Die FPGAs, February 2023, ACM (Association for Computing Machinery),
DOI: 10.1145/3543622.3573188.
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