Modeling two way concurrent buffer system using timed automata in UPPAAL

Rohit Mishra, Md Zeeshaan, Sanjay Singh
  • October 2012, Institute of Electrical & Electronics Engineers (IEEE)
  • DOI: 10.1109/wict.2012.6409193

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http://dx.doi.org/10.1109/wict.2012.6409193

The following have contributed to this page: Sanjay Singh