Fully depleted Silicon-On-Insulator with back bias and strain for low power and high performance applications

F. Andrieu, O. Weber, S. Baudot, C. Fenouillet-Beranger, O. Rozeau, J. Mazurier, P. Perreau, J. Eymery, O. Faynot
  • June 2010, Institute of Electrical & Electronics Engineers (IEEE)
  • DOI: 10.1109/icicdt.2010.5510295

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The following have contributed to this page: Dr Joel Eymery