What is it about?

This work presents an efficient and scalable Networks-on-Chip (NoC) topology termed as Cross-By-Pass-Mesh (CPB-Mesh). The proposed architecture is derived from the traditional Mesh topology by addition of cross-by-pass links in the network. The design and impact of adding cross-by-pass links on the topology is analysed in detail with the help of synthetic, hotspot as well as embedded traffic traces.

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Why is it important?

The advantages of proposed CBP-Mesh as compared to its competitor topologies include reduction in the network diameter, increase in bisection bandwidth, reduction in average numbers of hops, improvement in symmetry and regularity of the network. . The synthetic traffic traces and some real embedded system workloads are applied on the proposed CBP-Mesh and its competitor 2D based NoC topologies. The comparison of analytical results in terms of performance and costs for different network dimensions indicate that the proposed CBP-Mesh offers short latency, high throughput and good scalability at small increase in power and energy.


The proposed architecture can possibly help Network on Chip community in the selection and implementation of delay optimized 2D Mesh based NoC topologies.

Sheraz Anjum

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This page is a summary of: Efficient and scalable cross-by-pass-mesh topology for networks-on-chip , IET Computers & Digital Techniques, July 2017, the Institution of Engineering and Technology (the IET),
DOI: 10.1049/iet-cdt.2016.0184.
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