Assessment of interface traps in In$_{0.53}$Ga$_{0.47}$As FinFET with Gate-to-Source/Drain underlap for sub-14nm technology node to impede Short Channel effect

JAY PATHAK, Anand Darji
  • IET Circuits Devices & Systems, October 2018, the Institution of Engineering and Technology (the IET)
  • DOI: 10.1049/iet-cds.2018.5319

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http://dx.doi.org/10.1049/iet-cds.2018.5319

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