What is it about?
A dual-channel trench-gate tunnel FET (DCTG-TFET) is proposed and investigated. The gate of DCTG-TFET is placed vertically in a trench to create two channels which carry drain current in parallel. The proposed device dimensions are optimized to reduce channel resistance and tunnelling width for appreciable increase in ON-state current (ION). The performance of DCTG-TFET is analysed using two-dimensional simulations in the device simulator (ATLAS).
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Why is it important?
The proposed DCTGTFET provides one order of magnitude improvement in ION/IOF F current ratio and seventeen times reduction in subthreshold swing (SS) as compared to recently reported two-source-region (TRS) TFET structure.
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Reasearch Work
Mr Tripuresh Joshi
G B Pant Institute of Engineering & Technology, Pauri Garhwal
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This page is a summary of: Dual-Channel Trench-Gate (DCTG) Tunnel FETfor Improved ON-current and subthresholdSwing, Electronics Letters, August 2019, the Institution of Engineering and Technology (the IET),
DOI: 10.1049/el.2019.2219.
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