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The article presents a new augmented and improved MMBISR for SRAM using hybrid redundancy analysis (HRA). The presented algorithm is the augmented version of essential spare pivoting (ESP) and local repair most (LRM). The algorithm proposes the best solution by providing optimised set of row and column combination which were suitable for the repairing process. In the proposed redundancy analysis (RA) algorithm, the fault dictionary can be updated or fixed concurrently, according to MBIST needs and supplied control signals. The row and column pivots and repair requests are also serviced according to precedency list prepared by the comparing actions. The comparative analysis with LRM and ESP-RA algorithms shows that the proposed algorithm has reduced complexity and tracing time in terms of implementation and in terms of finding row and column pivots. For the implementation, a MBISR hardware structure is designed and tested using suitable VHDL descriptions that were targeted for Virtex-5, xc5vlx30 FPGA. The results were also justified that the proposed algorithm is quite effective as the repair rate is increased up to 4% compared to the ESP. However, some nominal area penalty is observed as compared to ESP.

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Memory Testing and Repair Strategies

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modified memory built in self-repair

Dr. Aditya Kumar Singh Pundir
Arya College of Engineering and Information Technology

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This page is a summary of: A Novel Modified Memory Built in Self-Repair (MMBISR) for SRAM using Hybrid Redundancy-Analysis Technique, IET Circuits Devices & Systems, April 2019, the Institution of Engineering and Technology (the IET), DOI: 10.1049/iet-cds.2018.5218.
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