Use of WKB approximation for analytical boundary conditions in numerical solution of Schrödinger equation: application to semiconductor-high-k dielectric interfaces

Amr M. Bayoumi
  • International Journal of Numerical Modelling Electronic Networks Devices and Fields, July 2015, Wiley
  • DOI: 10.1002/jnm.2084


What is it about?

Boundary conditions are crucial for proper numerical simulation of electron wavefunctions, especially with iterative techniques used to solve Schrödinger’s equation, such as the shooting method combined with Numerov’s integration. The WKB approximation has been used in the current work to calculate the wavefunction slope at the semiconductor–dielectric interface, because it does not depend on slope at the previous point, and depends on the actual potential structure, rather than asymptotic boundary conditions. An analytical simplification for the WKB-based slope of the wavefunction at the Si–dielectric interface has been developed, with very small errors. This can be used to speed the numerical simulations, by using realistic boundary conditions, which has an analytical closed form during iteration. The accuracy of this expression does not depend on issues such as grid size. This approach should be used only next to the interface to avoid error propagation with distance within the potential barrier. It was verified that it is especially suitable for semiconductor–dielectric interfaces such as the HfO2-SiO2 highdielectric constant gate stacks used in CMOS silicon technology. An application for using these boundary conditions was implemented into an MOS capacitor quantum mechanical simulator and is available for public domain use. This simulator was used to demonstrate results of the wavefunction penetration into the dielectric for the two silicon ellipsoids, in a dielectric with effective oxide thickness of 0.7 nm, corresponding to the prediction for the 10nm CMOS technology node. C-V data have shown the effects of wavefunction penetration on inversion capacitance. It was also applied to a dual gate FETs with fin thickness of 5 nm and high-k dielectric of 0.5nm equivalent oxide thickness.

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The following have contributed to this page: Dr Amr M Bayoumi