Dr Francesco Centurelli

All Stories

1. 
   High-Accuracy Low-Cost Generalized Complex Pruned Volterra Models for Nonlinear Calibration

   Article • IEEE Transactions on Circuits and Systems I Regular Papers, September 2023, Institute of Electrical & Electronics Engineers (IEEE)

   Dr Francesco Centurelli

2. 
   Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

   Article • Chips, August 2023, MDPI AG

   Dr Francesco Centurelli

3. 
   A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

   Article • Journal of Low Power Electronics and Applications, May 2023, MDPI AG

   Dr Francesco Centurelli

4. 
   A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow

   Article • Applied Sciences, April 2023, MDPI AG

   Dr Francesco Centurelli

5. 
   A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C

   Article • Electronics, February 2023, MDPI AG

   Dr Francesco Centurelli

6. 
   A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits

   Article • IEEE Transactions on Circuits and Systems I Regular Papers, February 2023, Institute of Electrical & Electronics Engineers (IEEE)

   Dr Francesco Centurelli

7. 
   A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations

   Article • IEEE Access, January 2023, Institute of Electrical & Electronics Engineers (IEEE)

   Dr Francesco Centurelli

8. 
   A Novel Parallel Digitizer With a Pulseless Mixing-Filtering-Processing Architecture and Its Implementation in a SiGe HBT Technology at 40GS/s

   Article • IEEE Access, January 2023, Institute of Electrical & Electronics Engineers (IEEE)

   Dr Francesco Centurelli

9. 
   An Improved Strong Arm Comparator with Integrated Static Preamplifier

   Article • IEEE Access, January 2023, Institute of Electrical & Electronics Engineers (IEEE)

   Dr Francesco Centurelli

10. 
    Enabling ULV Fully Synthesizable Analog Circuits: The BA Cell, a Standard-Cell-Based Building Block for Analog Design

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, December 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

11. 
    A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs

    Article • Electronics, November 2022, MDPI AG

    Dr Francesco Centurelli

12. 
    Methods for Model Complexity Reduction for the Nonlinear Calibration of Amplifiers Using Volterra Kernels

    Article • Electronics, September 2022, MDPI AG

    Dr Francesco Centurelli

13. 
    High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain

    Article • June 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

14. 
    Sub-μW Front-End Low Noise Amplifier for Neural Recording Applications

    Article • June 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

15. 
    Characterization-oriented design of E-band Variable-Gain Amplifiers in BiCMOS technology

    Article • May 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

16. 
    A Standard-Cell-Based CMFB for Fully Synthesizable OTAs

    Article • Journal of Low Power Electronics and Applications, May 2022, MDPI AG

    Dr Francesco Centurelli

17. 
    80 dB tuning range transimpedance amplifier exploiting the Switched-Resistor approach

    Article • AEU - International Journal of Electronics and Communications, May 2022, Elsevier

    Dr Francesco Centurelli

18. 
    SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends

    Article • April 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

19. 
    A New Fully Closed-Loop, High-Precision, Class-AB CCII for Differential Capacitive Sensor Interfaces

    Article • Electronics, March 2022, MDPI AG

    Dr Francesco Centurelli

20. 
    Low power class-AB VCII with extended dynamic range

    Article • AEU - International Journal of Electronics and Communications, March 2022, Elsevier

    Dr Francesco Centurelli

21. 
    A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

    Article • Journal of Low Power Electronics and Applications, February 2022, MDPI AG

    Dr Francesco Centurelli

22. 
    An Ultra-Low-Voltage class-AB OTA exploiting local CMFB and Body-to-Gate interface

    Article • AEU - International Journal of Electronics and Communications, February 2022, Elsevier

    Dr Francesco Centurelli

23. 
    A SiGe HBT 6th-Order 10 GHz Inductor-Less Anti-Aliasing Low-Pass Filter for High-Speed ATI Digitizers

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, January 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

24. 
    A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs

    Article • IEEE Access, January 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

25. 
    A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

    Article • IEEE Access, January 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

26. 
    General Approach to the Calibration of Innovative MFP Multichannel Digitizers

    Article • IEEE Transactions on Instrumentation and Measurement, January 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

27. 
    A class-AB linear transconductor with enhanced linearity

    Article • AEU - International Journal of Electronics and Communications, October 2021, Elsevier

    Dr Francesco Centurelli

28. 
    An E-band Variable Gain Amplifier with 24 dB-control range and 80 to 100 GHz 1 dB bandwidth in SiGe BiCMOS technology

    Article • Frequenz, September 2021, De Gruyter

    Dr Francesco Centurelli

29. 
    Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, September 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

30. 
    Distributed switched-resistor approach for high-Q biquad filters

    Article • AEU - International Journal of Electronics and Communications, August 2021, Elsevier

    Dr Francesco Centurelli

31. 
    A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

    Article • Electronics, July 2021, MDPI AG

    Dr Francesco Centurelli

32. 
    A New VCII Application: Sinusoidal Oscillators

    Article • Journal of Low Power Electronics and Applications, July 2021, MDPI AG

    Dr Francesco Centurelli

33. 
    0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

    Article • Electronics, June 2021, MDPI AG

    Dr Francesco Centurelli

34. 
    A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML

    Article • May 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

35. 
    A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, May 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

36. 
    A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

    Article • Journal of Low Power Electronics and Applications, April 2021, MDPI AG

    Dr Francesco Centurelli

37. 
    A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier

    Article • Applied Sciences, March 2021, MDPI AG

    Dr Francesco Centurelli

38. 
    Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, February 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

39. 
    A Detailed Model of the Switched-Resistor Technique

    Article • IEEE Open Journal of Circuits and Systems, January 2021, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

40. 
    A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS

    Article • Electronics, November 2020, MDPI AG

    Dr Francesco Centurelli

41. 
    A revision of the theory of THz detection by MOS-FET in the light of the self-mixing model in the substrate

    Article • November 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

42. 
    CMOS integrated system for Terahertz Detection

    Article • November 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

43. 
    A revision of the theory of THz detection by MOSFET in the light of the self-mixing model

    Article • September 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

44. 
    Low power switched-resistor band-pass filter for neural recording channels in 130nm CMOS

    Article • Heliyon, August 2020, Elsevier

    Dr Francesco Centurelli

45. 
    A low-voltage class-AB OTA exploiting adaptive biasing

    Article • AEU - International Journal of Electronics and Communications, July 2020, Elsevier

    Dr Francesco Centurelli

46. 
    An improved reversed miller compensation technique for three‐stage CMOS OTAs with double pole‐zero cancellation and almost single‐pole frequency response

    Article • International Journal of Circuit Theory and Applications, June 2020, Wiley

    Dr Francesco Centurelli

47. 
    Delay models and design guidelines for MCML gates with resistor or PMOS load

    Article • Microelectronics Journal, May 2020, Elsevier

    Dr Francesco Centurelli

48. 
    Low‐power class‐AB 4 th ‐order low‐pass filter based on current conveyors with dynamic mismatch compensation of biasing errors

    Article • International Journal of Circuit Theory and Applications, April 2020, Wiley

    Dr Francesco Centurelli

49. 
    10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

    Article • Electronics, March 2020, MDPI AG

    Dr Francesco Centurelli

50. 
    A low-power class-AB Gm-C biquad stage in CMOS 40nm technology

    Article • November 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

51. 
    0.6‐V CMOS cascode OTA with complementary gate‐driven gain‐boosting and forward body bias

    Article • International Journal of Circuit Theory and Applications, September 2019, Wiley

    Dr Francesco Centurelli

52. 
    High‐gain, high‐CMRR class AB operational transconductance amplifier based on the flipped voltage follower

    Article • International Journal of Circuit Theory and Applications, January 2019, Wiley

    Dr Francesco Centurelli

53. 
    A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, November 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

54. 
    A 10 GHz inductorless active SiGe HBT lowpass filter

    Article • International Journal of RF and Microwave Computer-Aided Engineering, October 2018, Hindawi Publishing Corporation

    Dr Francesco Centurelli

55. 
    Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS

    Article • AEU - International Journal of Electronics and Communications, August 2018, Elsevier

    Dr Francesco Centurelli

56. 
    A 0.6V class-AB rail-to-rail CMOS OTA exploiting threshold lowering

    Article • Electronics Letters, June 2018, the Institution of Engineering and Technology (the IET)

    Dr Francesco Centurelli

57. 
    A fully-differential class-AB OTA with CMRR improved by local feedback

    Article • September 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

58. 
    Class-AB current conveyors based on the FVF

    Article • September 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

59. 
    On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks

    Article • September 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

60. 
    Power-efficient dynamic-biased CCII

    Article • September 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

61. 
    The AB-CCII, a novel adaptive biasing LV-LP current conveyor architecture

    Article • AEU - International Journal of Electronics and Communications, September 2017, Elsevier

    Dr Francesco Centurelli

62. 
    Reconfigurable low voltage inverter-based sample-and-hold amplifier

    Article • June 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

63. 
    Fully Differential Class-AB OTA with Improved CMRR

    Article • Journal of Circuits System and Computers, April 2017, World Scientific Pub Co Pte Lt

    Dr Francesco Centurelli

64. 
    Calibration of pipeline ADC with pruned Volterra kernels

    Article • Electronics Letters, August 2016, the Institution of Engineering and Technology (the IET)

    Danilo Ruscio, Dr Francesco Centurelli

65. 
    Blind and reference channel-based time interleaved ADC calibration schemes: a comparison

    Article • July 2016, SPIE

    Dr Francesco Centurelli

66. 
    A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier

    Article • June 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

67. 
    Calibrating sample and hold stages with pruned Volterra kernels

    Article • Electronics Letters, December 2015, the Institution of Engineering and Technology (the IET)

    Dr Francesco Centurelli

68. 
    Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption

    Article • International Journal of Circuit Theory and Applications, July 2015, Wiley

    Dr Francesco Centurelli

69. 
    Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks

    Article • Journal of Cryptographic Engineering, April 2015, Springer Science + Business Media

    Dr Francesco Centurelli

70. 
    Feed array metrology and correction layer for large antenna systems in ASIC mixed signal technology

    Article • August 2014, SPIE

    Dr Francesco Centurelli

71. 
    Using feed array networks to control distortions in antenna reflector for astrophysical radio-astronomy

    Article • August 2014, SPIE

    Dr Francesco Centurelli

72. 
    Cosmic non-TEM radiation and synthetic feed array sensor system in ASIC mixed signal technology

    Article • August 2014, SPIE

    Dr Francesco Centurelli

73. 
    Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer

    Article • June 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

74. 
    A wideband amplifier topology based on positive capacitive feedback

    Article • Microelectronics Journal, January 2014, Elsevier

    Dr Francesco Centurelli

75. 
    An improved common-mode feedback loop for the differential-difference amplifier

    Article • Analog Integrated Circuits and Signal Processing, September 2012, Springer Science + Business Media

    Dr Francesco Centurelli

76. 
    Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, July 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

77. 
    An improved common-mode feedback loop for the differential-difference amplifier

    Article • November 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

78. 
    A class-AB flipped voltage follower output stage

    Article • August 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

79. 
    A class-AB very low voltage amplifier and sample & hold circuit

    Article • August 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

80. 
    A very low-voltage differential amplifier for opamp design

    Article • August 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

81. 
    An MDAC architecture with low sensitivity to finite opamp gain

    Article • August 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

82. 
    Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, June 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

83. 
    Near-optimum switched capacitor sample-and-hold circuit

    Article • November 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

84. 
    Extraction of CAD-compatible statistical nonlinear models of GaAs HEMT MMICs

    Article • Microwave and Optical Technology Letters, June 2009, Wiley

    Dr Francesco Centurelli

85. 
    Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, June 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

86. 
    A wideband high-CMRR single-ended to differential converter

    Article • Analog Integrated Circuits and Signal Processing, December 2008, Springer Science + Business Media

    Dr Francesco Centurelli

87. 
    Switched Capacitor Sample-and-Hold Circuit with Input Signal Range beyond Supply Voltage

    Article • November 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

88. 
    A Gain-Enhancing Technique for Very Low-Voltage Amplifiers

    Article • May 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

89. 
    A low-power sample-and-hold circuit based on a switched-opamp technique

    Article • January 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

90. 
    A Simple Technique for Fast Digital Background Calibration of A/D Converters

    Article • EURASIP Journal on Advances in Signal Processing, November 2007, Springer Science + Business Media

    Dr Francesco Centurelli

91. 
    CMOS High-CMRR Current Output Stages

    Article • IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing, September 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Alfio Dario Grasso, Dr Francesco Centurelli

92. 
    CMOS Miller OTA with Body-Biased Output Stage

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Alfio Dario Grasso, Dr Francesco Centurelli

93. 
    A Sample-and-Hold Circuit with Very Low Gain Error for Time Interleaving Applications

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

94. 
    Power-constrained Bandwidth Optimization in Cascaded Open-loop Amplifiers

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

95. 
    A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data

    Article • IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications, August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

96. 
    A distortion model for pipeline Analog-to-Digital converters

    Article • May 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

97. 
    Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

    Article • Analog Integrated Circuits and Signal Processing, April 2006, Springer Science + Business Media

    Dr Francesco Centurelli

98. 
    A Novel Dual-Output CCII-Based Single-Ended to Differential Converter

    Article • Analog Integrated Circuits and Signal Processing, April 2005, Springer Science + Business Media

    Dr Francesco Centurelli

99. 
    A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, February 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Francesco Centurelli

100. 
     An active balun for high-CMRR IC design

     Article • January 2005, Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

101. 
     Analytic transient solution of SCFL logic gates

     Article • International Journal of Circuit Theory and Applications, January 2005, Wiley

     Dr Francesco Centurelli

102. 
     Behavioral model of a noisy VCO for efficient time-domain simulation

     Article • Microwave and Optical Technology Letters, January 2004, Wiley

     Dr Francesco Centurelli

103. 
     A new procedure for nonlinear statistical model extraction of GaAs FET-integrated circuits

     Article • International Journal of RF and Microwave Computer-Aided Engineering, August 2003, Wiley

     Dr Francesco Centurelli

104. 
     Model of flicker noise effects on phase noise in oscillators

     Article • May 2003, SPIE

     Dr Francesco Centurelli

105. 
     High-CMRR CMOS current output stage

     Article • Electronics Letters, January 2003, the Institution of Engineering and Technology (the IET)

     Dr Francesco Centurelli

106. 
     A bootstrap technique for wideband amplifiers

     Article • IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications, October 2002, Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

107. 
     A new model to analyze the effects of noise in a real oscillator

     Article • Microwave and Optical Technology Letters, January 2002, Wiley

     Dr Francesco Centurelli

108. 
     A bandwidth-compensated transimpedance amplifier for multigigabit optical receivers

     Article • Microwave and Optical Technology Letters, January 2001, Wiley

     Dr Francesco Centurelli

109. 
     A compact 3R-receiver module for short-haul SDH STM-16 systems

     Article • Journal of Lightwave Technology, January 2001, Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

110. 
     A new topology for a transimpedance amplifier with postfabrication bandwidth adjustment

     Article • Microwave and Optical Technology Letters, April 2000, Wiley

     Dr Francesco Centurelli

111. 
     A synthesis-oriented approach to design microwave multidevice amplifiers with a prefixed stability margin

     Article • IEEE Microwave and Guided Wave Letters, March 2000, Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

112. 
     A novel bias-dependent rational model for MESFET and HEMT devices

     Article • Microwave and Optical Technology Letters, January 2000, Wiley

     Dr Francesco Centurelli

113. 
     A low-power Clock and Data Recovery circuit for 2.5 Gb/s SDH receivers

     Article • January 2000, Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

114. 
     A synthesis-oriented conditional stability criterion for microwave multidevice circuits with complex termination impedances

     Article • IEEE Microwave and Guided Wave Letters, January 2000, Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

115. 
     Design of a transimpedance amplifier for 10 Gbit/s optical receivers with a new topology of active balun

     Article • Microwave and Optical Technology Letters, January 2000, Wiley

     Dr Francesco Centurelli

116. 
     A novel topology for four-quadrant GaAs monolithic multipliers

     Article • Microwave and Optical Technology Letters, May 1999, Wiley

     Dr Francesco Centurelli

117. 
     <title>Monolithic 2.5-Gb/s clock and data recovery circuit based on silicon bipolar technology</title>

     Article • September 1998, SPIE

     Dr Francesco Centurelli

118. 
     A 10 Gb/s CDR in SiGe BiCMOS commercial technology with multistandard capability

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr jesus A Guinea, Dr Francesco Centurelli

119. 
     A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations

     Article • Springer Science + Business Media

     Dr Francesco Centurelli

120. 
     A model for the distortion due to switch on-resistance in sample-and-hold circuits

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

121. 
     Validation of a Statistical Non-Linear Model of GaAs HEMT MMIC's by Hypothesis Testing and Principal Components Analysis

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

122. 
     High-speed CMOS-to-ECL pad driver in 0.18μm CMOS

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

123. 
     A high-speed low-voltage phase detector for clock recovery from NRZ data

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

124. 
     An accurate behavioral model of phase detectors for clock recovery circuits

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

125. 
     Current output stage with improved CMRR

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

126. 
     A tree-like amplifier architecture for large gain-bandwidth product

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

127. 
     Bipolar differential cell with improved bandwidth performance

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

128. 
     A new topology of controlled C/sup 3/A differentiator for multi-Gb/s optical applications

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli

129. 
     Input-matching and offset-compensation network for limiting amplifiers in optical communication systems

     Article • Institute of Electrical & Electronics Engineers (IEEE)

     Dr Francesco Centurelli