All Stories

  1. Design of ultra low power sub threshold Dgfinfet based VC0

    Article • International Journal of Electronics, September 2018, Taylor & Francis

    Rupali Walunj, sachin Pabale

  2. Challenges in design of sub threshold clock circuit

    Article • Australian Journal of Electrical & Electronics Engineering, July 2018, Taylor & Francis

    Rupali Walunj

  3. Ultra Low Power Robust VCO

    Article • Australian Journal of Electrical & Electronics Engineering, June 2018, Taylor & Francis

    Rupali Walunj, sachin Pabale

  4. Design of ULP VCO

    Article • February 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Rupali Walunj