All Stories

  1. SRAM cell aging (BTI related) monitoring circuitry and technique.

    Article • July 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Yiorgos Tsiatouhas

  2. Periodic Bias-Temperature Instability monitoring in SRAM cells

    Article • May 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Yiorgos Tsiatouhas

  3. Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs

    Article • IEEE Transactions on Computers, July 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Yiorgos Tsiatouhas

  4. Soft error immune latch under SEU related double-node charge collection

    Article • July 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Yiorgos Tsiatouhas

  5. On resistive open defect detection in DRAMs: The charge accumulation effect

    Article • May 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Yiorgos Tsiatouhas

  6. Soft error interception latch: double node charge sharing SEU tolerant design

    Article • Electronics Letters, February 2015, the Institution of Engineering and Technology (the IET)

    Yiorgos Tsiatouhas

  7. NBTI aging tolerance in pipeline based designs NBTI

    Article • July 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Yiorgos Tsiatouhas

  8. Memory-Less Pipeline Dynamic Circuit Design Technique

    Article • July 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Yiorgos Tsiatouhas

  9. Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing

    Article • January 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Yiorgos Tsiatouhas

  10. Design of stuck-open fault testable CMOS complex gates

    Article • Electronics Letters, January 1996, the Institution of Engineering and Technology (the IET)

    Yiorgos Tsiatouhas