All Stories

  1. Design and Analysis of a 1-Bit Comparator for Low Power VLSI Systems
  2. High-Resolution Time Amplifier-Based Time-to-Digital Converter
  3. Performance analysis of low-power multi-threshold CMOS-based 10T SRAM cell
  4. Performance Analysis of 4-Bit Hybrid Low Power Carry Select Adder using FinFET Technology
  5. Performance Analysis of LCNMOS and MTCMOS-Based Low-Power 28 T Full Adders
  6. Area and Power Optimized RTL to GDS II Flow of a Telecommunication Receiver Core
  7. Performance Evaluation of Adder Topologies Integrated into MAC Units and MLP Model for Digit Recognition
  8. 8T-based Low-power CAM cell for Binary CAM Arrays
  9. QRS Peak Detection Using Statistical False Peak Elimination and Derivative Search Back
  10. Area and energy optimized Hamming encoder and decoder for nano-communication
  11. Area and Power Efficient AVLS-TSPC-Based Diffused Bit Generator for Key Generation
  12. Design and Analysis of Power and Area Efficient 4–2 Compressor Circuit for Tree Multiplier
  13. FPGA-Based Efficient MLP Neural Network for Digit Recognition
  14. Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider
  15. PCA and MLE-Based Statistical Factor Models for Asset Pricing
  16. AVLS-based 32/33 Pre-scaler for frequency dividers
  17. TSPC-AVLS Based Low-Power 16/17 Dual Modulus Pre-Scaler Design
  18. Automated Triaging of Gate Run Test Results using Humio Tool
  19. Secure Hashing using BCrypt for Cryptographic Applications
  20. Transition of Cloud Computing from Traditional Applications to the Cloud Native Approach
  21. Secure Bootloader for Connectivity MCU
  22. Low-Power Phase Frequency Detector Using Hybrid AVLS and LECTOR Techniques for Low-Power PLL
  23. Performance Evaluation of ML Algorithms for Disease Prediction Using DWT and EMD Techniques
  24. Face Mask Detection and Face Recognition of Unmasked People in Organizations
  25. Area and Energy Efficient QCA Based Compact Serial Concatenated Convolutional Code Encoder
  26. Performance Analysis of Machine Learning Algorithms in Detecting and Mitigating Black and Gray Hole Attacks
  27. Design and Simulation of a Direct-PSK Based Telecommand Receiver for Small Satellite
  28. Area and Energy Optimized QCA-Based Binary to Gray Code Converters
  29. Area and Energy Opimized QCA Based Shuffle-Exchange Network with Multicast and Broadcast Configuration
  30. Low Power Square Root Carry Select Adder Using AVLS-TSPC-Based D Flip-Flop
  31. Analysis of QCA-Based Serial Concatenated Convolution Coding Encoder for Error Correction
  32. Data and Bandwidth Analysis of CAN Bus in a System Using MATLAB
  33. Design and Implementation of Phase Frequency Detectors for Low-Power PLL
  34. Low-power modified phase-locked loop using AVLS technique for biomedical applications
  35. Design and Implementation of High Frequency and Low-Power Phase-locked Loop
  36. A Low Power Diffused Bit Generator as a TRNG for Cryptographic Key Generation
  37. Design of Compact and Energy Efficient Banyan Network for Nano Communication
  38. Design and Implementation of Power and Area Efficient Phase Frequency Detector
  39. Generation of Flash Containers in PDX Format for Automotive Secure Gateway
  40. Performance Analysis of MD5 and SHA-256 Algorithms to Maintain Data Integrity
  41. PFD with Dead zone based Low Power Modified Phase Lock Loop using AVLS Technique
  42. Area and Energy Efficient QCA based Decoder
  43. Low power add-one circuit IPGL based high speed square root carry select adder
  44. Adaptive Beamforming Using LMS Algorithm for Planar Arrays and Subarrays
  45. MEC S-box based PRESENT Lightweight Cipher for Enhanced Security and Throughput
  46. Development of Self Assisted Voice Module for Visually Impaired
  47. Estimation of Reverberation Time by Performing Acoustic Echo Cancellation Considering Near-end and Far-end Speech Signals
  48. Design and Analysis of QCA based Area Efficient 4×8 SRAM Array
  49. Design of QCA Based Three-Stage Pseudo Random Number Generator
  50. Performance Evaluation of Various Beamforming Techniques for Phased Array Antennas
  51. Design of Low Power Reduced Complexity Wallace Tree Multiplier Using Positive Feedback Adiabatic Logic
  52. Low-Power 8-Bit Adiabatic Barrel Shifter for DSP Applications
  53. A Novel QCA based Compact Scan Flip-flop for Digital Design Testing
  54. Low Power AVLS-TSPC based 2/3 Pre-Scaler
  55. Compact QCA based JK Flip-Flop for Digital System
  56. Low-Power PFAL Based Speculative Han-Carlson Adder for Signal Processing Applications
  57. Design of Low-Power Square Root Carry Select Adder and Wallace Tree Multiplier Using Adiabatic Logic
  58. Development of Hybrid Algorithm for Masquerading Sink Node Location in WSN
  59. Design and Analysis of Compact QCA Based 4-Bit Serial-Parallel Multiplier
  60. energy-efficient, coalition game theory based hierarchical routing protocol for WSNs
  61. Design of Low Power and High-Speed 16-bit Square Root Carry Select Adder using AL
  62. Design of Compact Vedic Multiplier for High Performance Circuits
  63. Design and Analysis of Low-Power 16-bit Parallel-Prefix Adiabatic Adders
  64. Design and performance analysis of modified unsigned braun and signed Baugh-Wooley multiplier
  65. Development of LIN 2.1 Driver with SAE Standards for RL78 Microcontroller
  66. Performance analysis of MANET routing protocols for military applications
  67. High spatial resolution hyperspectral image using fusion technique
  68. Impact of ERB and bark scales on perceptual distortion based near-end speech enhancement
  69. Improving the network lifetime of a wireless sensor network using clustering techniques
  70. Network performance analysis of MANET routing protocols with various mobility models
  71. Hardware validation for intelligibility improvement of NELE on DSP processor
  72. Design of low power 8-bit carry select adder using adiabatic logic
  73. Design of low power barrel shifter and vedic multiplier with kogge-stone adder using reversible logic gates
  74. Automation of device validation using digital power technology and PMBus communication
  75. A novel method of wideband acquisition and anti-sideband lock in PM receivers using FFT
  76. Design and performance analysis of FEC schemes in OFDM communication system
  77. Implementation of operand decomposition in signed logarithmic multipliers
  78. Lower and higher critical band enhancement to attain intelligibility improvement in noisy environment
  79. Approach to enhance the speech signal to mitigate background noise in Mobile phone.
  80. Design and Development of High-speed Data Acquisition System with Cyclone FPGA
  81. Dominant Frequency Enhancement of Speech Signal to Improve Intelligibility and Quality
  82. Selective Frequency Enhancement of Speech Signal for Intelligibility Improvement in Presence of Near-end Noise
  83. Speech enhancement using temporal masking in presence of near-end noise
  84. Design of area and power efficient complex number multiplier
  85. Speech enhancement to overcome the effect of near-end noise in mobile phones using psychoacoustics
  86. FPGA implementation for generation of six phase pulse compression sequences
  87. Signed fixed-point multiplier for DSP using vertically and crosswise algorithm
  88. Speech Enhancement Algorithm to Reduce the Effect of Background Noise in Mobile Phones
  89. Low Complexity Speech Enhancement Algorithm for Improved Perception in Mobile Devices