All Stories

  1. Energy-Efficient Hardware for Language Guided Reinforcement Learning
  2. ICNN
  3. Full-Lock
  4. Adversarial Attack on Microarchitectural Events based Malware Detectors
  5. Mitigating the Performance and Quality of Parallelized Compressive Sensing Reconstruction Using Image Stitching
  6. On Custom LUT-based Obfuscation
  7. Threats on Logic Locking
  8. Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering
  9. Optimal Allocation of Computation and Communication in an IoT Network
  10. Efficient utilization of adversarial training towards robust machine learners and its analysis
  11. System and Architecture Level Characterization of Big Data Applications on Big and Little Core Server Architectures
  12. Comprehensive assessment of run-time hardware-supported malware detection using general and ensemble learning
  13. Heterogeneous HMC+DDRx Memory Management for Performance-Temperature Tradeoffs
  14. Low Overhead CS-Based Heterogeneous Framework for Big Data Acceleration
  15. LESS: Big data sketching and Encryption on low power platform
  16. Analyzing Hardware Based Malware Detectors
  17. Hybrid STT-CMOS designs for reverse-engineering prevention
  18. Heterogeneous chip multiprocessor architectures for big data applications
  19. ElasticCore
  20. Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory
  21. Just-in-time component-wise power and thermal modeling
  22. Accelerating Machine Learning Kernel in Hadoop Using FPGAs
  23. Accelerating Big Data Analytics Using FPGAs
  24. Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation
  25. Dynamically heterogeneous cores through 3D resource pooling
  26. Adaptive techniques for leakage power management in L2 cache peripheral circuits
  27. Reducing leakage power in peripheral circuits of L2 caches
  28. Reducing the Instruction Queue Leakage Power in Superscalar Processors