All Stories

  1. SATLLM: A Sparsity-aware Accelerator for Ternary-Weight Large Language Models
  2. Graph Neural Network based Initialization for Timing Driven Placement
  3. Variation-aware Analog Circuit Design via Contextual Modeling and Robust Optimization
  4. ChatArch: A Knowledge-driven Graph-of-thought LLM Framework for Processor Architecture Optimization
  5. ActiveEye: Enabling Continuous and Responsive Video Understanding for Smart Eyewear Systems
  6. Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis
  7. GTN-Path: Efficient Path Timing Prediction through Waveform Propagation with Graph Transformer
  8. AcclMT: A Highly Resource-Efficient and Flexible Poseidon Hash-Based Merkle Tree Architecture
  9. Hierarchical Integration of Reinforcement Learning and Optimization Algorithms for Time-Efficient Design Automation of Complex Analog Circuit
  10. TL-CSE: Microarchitecture-Compiler Co-design Space Exploration via Transfer Learning
  11. Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis
  12. FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible Sparsity
  13. Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
  14. AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis
  15. The Power of Graph Signal Processing for Chip Placement Acceleration
  16. PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication
  17. Gypsophila: A Scalable and Bandwidth-Optimized Multi-Scalar Multiplication Architecture
  18. Efficient ILT via Multigrid-Schwartz Method
  19. HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing
  20. EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration
  21. Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model
  22. HMNTT: A Highly Efficient MDC-NTT Architecture for Privacy-preserving Applications
  23. Aries: A DNN Inference Scheduling Framework for Multi-core Accelerators
  24. Can Large Language Models Be Good Companions?
  25. FullSparse: A Sparse-Aware GEMM Accelerator with Online Sparsity Prediction
  26. D 3 PBO: D ynamic D omain D ecomposition based P arallel B aye...
  27. MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational Amplifier
  28. Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Network: Enhancing Circuit Reliability under Environmental Variation
  29. CASES
  30. Graph Representation Learning for Microarchitecture Design Space Exploration
  31. TPNoC: An Efficient Topology Reconfigurable NoC Generator
  32. Guest Editor's Introduction: Machine Learning for VLSI Physical Design
  33. GraphPlanner: Floorplanning with Graph Neural Network
  34. Unveiling Causal Attention in Dogs' Eyes with Smart Eyewear
  35. ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid
  36. Efficient Layout Hotspot Detection via Neural Architecture Search
  37. LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces
  38. Floorplanning with graph attention
  39. Do Smart Glasses Dream of Sentimental Visions?
  40. Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization
  41. A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization
  42. An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis
  43. An efficient data reuse strategy for multi-pattern data access
  44. Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits
  45. Efficient performance modeling of analog integrated circuits via kernel density based sparse regression
  46. Subspace Trajectory Piecewise-Linear Model Order Reduction for Nonlinear Circuits
  47. Improved tangent space based distance metric for accurate lithographic hotspot classification