All Stories

  1. 1D Nanomaterial-Based Highly Stretchable Strain Sensors for Human Movement Monitoring and Human-Robotic Interactive Systems
  2. Stretchable Strain Sensors for Human Movement Monitoring
  3. Review—Energy Autonomous Wearable Sensors for Smart Healthcare: A Review
  4. Importance of Interconnects: A Technology-System-Level Design Perspective
  5. Emerging technologies and computing paradigms for the Internet of Everything applications. International Journal of Circuit, Theory, and Applications
  6. Investigation of Pt-Salt-Doped-Standalone- Multiwall Carbon Nanotubes for On-Chip Interconnect Applications
  7. Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs
  8. Editorial TVLSI Positioning—Continuing and Accelerating an Upward Trajectory
  9. Power-Supply Noise Analysis for Monolithic 3D ICs Using Electrical and Thermal Co-Simulation
  10. A high-reliability and low-power computing-in-memory implementation within STT-MRAM
  11. Atomistic- to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects
  12. Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint
  13. Understanding Electromigration in Cu-CNT Composite Interconnects: A Multiscale Electrothermal Simulation Study
  14. A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM
  15. Resistance Scaling of Cu Interconnect and Alternate Metal (Co, Ru) Benchmark toward sub 10nm Dimension
  16. Addressing the Thermal Issues of STT-MRAM From Compact Modeling to Design Techniques
  17. Progress on carbon nanotube BEOL interconnects
  18. Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances--Part I: Pristine MWCNT
  19. Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances--Part II: Impact of Charge Transfer Doping
  20. Physical Design for 3D Integrated Circuits
  21. A physics-based investigation of Pt-salt doped carbon nanotubes for local interconnects
  22. Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic
  23. Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application
  24. Atoms-to-circuits simulation investigation of CNT interconnects for next generation CMOS technology
  25. The impact of vacancy defects on CNT interconnects: From statistical atomistic study to circuit simulations
  26. Electrical performance of carbon-based power distribution networks with thermal effects
  27. Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era
  28. A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits
  29. Carbon Nanotubes for Interconnects
  30. Editorial
  31. Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM
  32. A Study of 3-D Power Delivery Networks With Multiple Clock Domains
  33. Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect
  34. Front matters
  35. Investigation of electrical and thermal properties of carbon nanotube interconnects
  36. Physical description and analysis of doped carbon nanotube interconnects
  37. Exploring Carbon Nanotubes for 3D Power Delivery Networks
  38. Electrothermal Analysis of Carbon Nanotubes Power Delivery Networks for Nanoscale Integrated Circuits
  39. A clustering technique for fast electrothermal analysis of on-chip power distribution networks
  40. Investigation of the power-clock network impact on adiabatic logic
  41. Quantitative evaluation of reliability and performance for STT-MRAM
  42. Present and future prospects of carbon nanotube interconnects for energy efficient integrated circuits
  43. Reliability and performance evaluation for STT-MRAM under temperature variation
  44. Guest Editorial
  45. On Analysis of On-chip DC-DC Converters for Power Delivery Networks
  46. An architecture-level cache simulation framework supporting advanced PMA STT-MRAM
  47. Carbon-based Power Delivery Networks for nanoscale ICs: electrothermal performance analysis
  48. Message from the General and Program Chairs
  49. On the Performance Exploration of 3D NoCs with Resistive-Open TSVs
  50. A node clustering reduction scheme for power grids electrothermal analysis
  51. Towards a Digital Attribution Model: Measuring the Impact of Display Advertising on Online Consumer Behavior
  52. Evaluating a radiation monitor for mixed-field environments based on SRAM technology
  53. Investigation of horizontally aligned carbon nanotubes for efficient power delivery in 3D ICs
  54. An intra-cell defect grading tool
  55. Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults
  56. Test and diagnosis of power switches
  57. Timing-aware ATPG for critical paths with multiple TSVs
  58. On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs
  59. A novel method to mitigate TSV electromigration for 3D ICs
  60. Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains
  61. Analyzing resistive-open defects in SRAM core-cell under the effect of process variability
  62. Computing detection probability of delay defects in signal line tsvs
  63. Frequency domain power and thermal integrity analysis of 3D power delivery networks
  64. A built-in scheme for testing and repairing voltage regulators of low-power srams
  65. Effect-cause intra-cell diagnosis at transistor level
  66. Test Solution for Data Retention Faults in Low-Power SRAMs
  67. Why and How Controlling Power Consumption during Test: A Survey
  68. Defect analysis in power mode control logic of low-power SRAMs
  69. Through-Silicon-Via resistive-open defect analysis
  70. Failure Analysis and Test Solutions for Low-Power SRAMs
  71. Power-Aware Test Pattern Generation for At-Speed LOS Testing
  72. Power supply noise and ground bounce aware pattern generation for delay testing
  73. Enhancement of the ATLAS trigger system with a hardware tracker finder FTK
  74. Reliability and performance studies of DC-DC conversion powering scheme for the CMS pixel tracker at SLHC
  75. Proposal for the development of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)
  76. Performance studies of CMS Pixel Tracker using DC-DC conversion powering scheme
  77. Power distribution studies for CMS forward tracker
  78. Electromigration study of power-gated grids
  79. Power supply noise aware workload assignment for multi-core systems
  80. A study of reliability issues in clock distribution networks
  81. Exploration of carbon nanotubes for efficient power delivery
  82. Lumped electro-thermal modeling and analysis of carbon nanotube interconnects