What is it about?
The paper explains the different types of non volatile memories such as resistive, ferroelectric, magnetic, flash, phase change, memristors, and MEMS based. It also discusses the different architectures followed, such as crossbars, nand, nor flash architectures, and 1t1c, 2t2c FERAM architectures. It then reports on the progress made towards creating flexible versions of these memory types and provides comprehensive tables summarizing the benchmarking each of the main flexible memory categories. Finally it provides insights and highlights future challenges towards realizing flexible memories for the internet of things and the internet of everything.
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Why is it important?
It provides a comprehensive survey of works done on flexible non volatile memories and identifies major areas of progress and challenges that still persist.
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This page is a summary of: Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics, Electronics, July 2015, MDPI AG,
DOI: 10.3390/electronics4030424.
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Thin PZT‐Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications
A flexible version of traditional thin lead zirconium titanate ((Pb1.1Zr0.48Ti0.52O3)‐(PZT)) based ferroelectric random access memory (FeRAM) on silicon shows record performance in flexible arena. The thin PZT layer requires lower operational voltages to achieve coercive electric fields, reduces the sol‐gel coating cycles required (i.e., more cost‐effective), and, fabrication wise, is more suitable for further scaling of lateral dimensions to the nano‐scale due to the larger feature size‐to‐depth aspect ratio (critical for ultra‐high density non‐volatile memory applications). Utilizing the inverse proportionality between substrate's thickness and its flexibility, traditional PZT based FeRAM on silicon is transformed through a transfer‐less manufacturable process into a flexible form that matches organic electronics' flexibility while preserving the superior performance of silicon CMOS electronics. Each memory cell in a FeRAM array consists of two main elements; a select/access transistor, and a storage ferroelectric capacitor. Flexible transistors on silicon have already been reported. In this work, we focus on the storage ferroelectric capacitors, and report, for the first time, its performance after transformation into a flexible version, and assess its key memory parameters while bent at 0.5 cm minimum bending radius.
Study of harsh environment operation of flexible ferroelectric memory integrated with PZT and silicon fabric
Flexible memory can enable industrial, automobile, space, and smart grid centered harsh/extreme environment focused electronics application(s) for enhanced operation, safety, and monitoring where bent or complex shaped infrastructures are common and state-of-the-art rigid electronics cannot be deployed. Therefore, we report on the physical-mechanical-electrical characteristics of a flexible ferroelectric memory based on lead zirconium titanate as a key memory material and flexible version of bulk mono-crystalline silicon (100). The experimented devices show a bending radius down to 1.25 cm corresponding to 0.16% nominal strain (high pressure of ∼260 MPa), and full functionality up to 225 °C high temperature in ambient gas composition (21% oxygen and 55% relative humidity). The devices showed unaltered data retention and fatigue properties under harsh conditions, still the reduced memory window (20% difference between switching and non-switching currents at 225 °C) requires sensitive sense circuitry for proper functionality and is the limiting factor preventing operation at higher temperatures.
Supplementary Material Study of harsh environment operation of flexible ferroelectric memory integrated with PZT and silicon fabric
Fabrication flow of flexible PZT ferroelectric memory capacitors (a)-(g). Digital image shows the flexible silicon fabric with PZT based ferroelectric memory devices (h-top), scanning electron microscope (SEM) image shows 40 μm thick flexible silicon fabric with the memory devices (h-bottom left), and SEM zoomed-in image showing the marked up layers (h-bottom right). The ferroelectric memory storage cells were fabricated in a traditional way on bulk mono-crystalline Si (100) with 300 nm thermally grown silicon oxide SiO2 for electrical insulation. First, a bilayer of 10 nm Titanium (Ti)/ 100 nm Platinum (Pt) was sputtered on the thermal oxide to form the bottom electrode, followed by PZT layer formation and 100 nm Pt top electrode deposition. Ti was used for adhesion and Pt served as the common bottom electrode for the ferroelectric capacitors. Then, using sol-gel technique, four ceramic layers of PZT (Pb1.1Zr0.52Ti0.48O3) were spin-coated, giving a final thickness of 280 nm. Each layer was spun at 1500 revolutions per minute (rpm) for 35 seconds, and then thermally treated for pyrolysis at 350 °C for 8 minutes to evaporate the solvents. The second and fourth layers were treated with rapid thermal annealing (RTA) in argon for crystallization at 700 °C for 1 minute. The resulting PZT film was poly-crystalline with (110) as the preferred crystal orientation. To define the pattern of the ferroelectric capacitors, 4 µm thick AZ ECI3027 photoresist (PR) was spun at 1750 rpm for 30 s, soft baked at 100 °C for 60 s, and exposed at 200 mJ/cm2 constant energy, then patterned in AZ726 MIF developer for 60 s. The top Pt electrode and PZT were then etched using a timed physical Ar+ bombardment in a reactive ion etching (RIE) chamber at 10 mTorr, 150 W forward power and 300 W inductively coupled plasma (ICP) power to give the final patterned structures of square capacitors, 250 µm a side. Another layer of PR was then spin coated on top of the devices for protection and the wafer is flipped for soft etch back1. Finally, using a deep reactive ion etching (DRIE) utilizing the bosch process of successive SF6 silicon etching and C4F8 polymer deposition at -20 °C for less abrasive etching, the wafer material was subtracted down from 500 µm to 40 µm, for attaining flexibility. S2. Calculation of memory window The memory window is defined as the ratio of switching current (Isw) and non-switching current (Insw). For memory array operations, the resulting currents due to switching/non-switching is passed to a sense resistor, converted into a voltage level, and passed to a comparator circuitry to determine if the read state is a “0” or a “1” bit. S. Figure 2 shows the calculation of memory window at various temperatures, extracted from voltage-current vs. time plots.
Towards neuromorphic electronics: Memristors on foldable silicon fabric
The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge of building neuromorphic devices on structurally foldable platform with high integration density. We present a CMOS compatible fabrication process to demonstrate for the first time memristive devices fabricated on bulk monocrystalline silicon (100) which is next transformed into a flexible thin sheet of silicon fabric with all the pre-fabricated devices. This process preserves the ultra-high integration density advantage unachievable on other flexible substrates. In addition, the memristive devices are of the size of a motor neuron and the flexible/folded architectural form factor is critical to match brain cortex׳s folded pattern for ultra-compact design.
Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS
We present a comprehensive electrical performance assessment of hafnium silicate (HfSiOx) high-κ dielectric and titanium-nitride (TiN) metal-gate-integrated FinFET-based complementary-metal-oxide-semiconductor (CMOS) on flexible silicon on insulator. The devices were fabricated using the stateof-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied along and across the transistor channel lengths through a bending range of 0.5-5 cm radii for n-type and p-type FinFETs. Electrical measurements were carried out before and after bending, and all the bending measurements were taken in the actual flexed (bent) state to avoid relaxation and stress recovery. Global stress from substrate bending affects the devices in different ways compared with the well-studied uniaxial/biaxial localized strain. The global stress is dependent on the type of channel charge carriers, the orientation of the bending axis, and the physical gate length of the device. We, therefore, outline useful insights on the design strategies of flexible FinFETs in future free-form electronic applications.
Mechanical anomaly impact on metal-oxide-semiconductor capacitors on flexible silicon fabric
We report the impact of mechanical anomaly on high-κ/metal-oxide-semiconductor capacitors built on flexible silicon (100) fabric. The mechanical tests include studying the effect of bending radius up to 5 mm minimum bending radius with respect to breakdown voltage and leakage current of the devices. We also report the effect of continuous mechanical stress on the breakdown voltage over extended periods of times.
Highly Manufacturable Deep (Sub‐Millimeter) Etching Enabled High Aspect Ratio Complex Geometry Lego‐Like Silicon Electronics
A highly manufacturable deep reactive ion etching based process involving a hybrid soft/hard mask process technology shows high aspect ratio complex geometry Lego‐like silicon electronics formation enabling free‐form (physically flexible, stretchable, and reconfigurable) electronic systems.
Lego like silicon electronics fabricated with hybrid etching masks
Bulk micromachining techniques are commonly used for making high aspect ratio structures used in complementary metal oxide semiconductor (CMOS) technology, microelectromechanical systems (MEMS), dynamic random access memory (DRAM) capacitors, and 3D integrated circuits. These techniques generally utilize a hard mask – for example metal – material to withstand abrasive deep reactive ion etching (DRIE) that is used in bulk micromachining. However, the use of hard masks during deep etching (hundreds of microns) imposes some manufacturing limitations. A novel technique eliminates the disadvantages of using hard mask alone, which (a) can diffuse into the lower layers; (b) is hard to etch or etched using chemicals that are not environment friendly or convenient for device fabrication due to contamination and selectivity; and (c) affects the surface roughness of underlying layers during deposition and etching. "The novelty of our technique is the combination of using a soft and hard mask together in a single entity (a hybrid mask) during the deep etching and the reaped benefits in terms of combining resistance to prolonged etching, easy removal, and preservation of lower layers simultaneously," Muhammad Mustafa Hussain, an Associate Professor of Electrical Engineering at King Abdullah University of Science and Technology (KAUST), explains to Nanowerk. The different properties of positive and negative photoresist (photosensitive materials) in terms of how they respond to light and interact with developer chemicals can be used to transform one of them into an actual masking layer (sacrificial). For instance, if a negative photoresist is exposed to ultra-violet (UV) light it becomes insoluble in developer. This enabled the KAUST team to deposit and pattern another mask (hard mask) using positive photoresist and patterning the positive photoresist in developer without affecting the negative photoresist – which is insoluble in developer after UV exposure and separated by a hard mask from the positive photoresist. The researchers have published their findings in Small ("Highly Manufacturable Deep (Sub-Millimeter) Etching Enabled High Aspect Ratio Complex Geometry Lego-Like Silicon Electronics").
Lego-like electronics
Researchers present a new etching technique that combines a soft and hard mask in a single entity. Lakshini Mendis Scientists have created a hybrid technique where, according to them, “anyone with a basic knowledge of electronics will be able to easily assemble application-oriented electronic systems.” Mohamed Ghoneim and Muhammad Hussain, from King Abdullah University of Science and Technology, Saudi Arabia, want to promote the advent of DIY electronics. Assembling electronics is currently a sophisticated, complex method, says Hussain, the principal investigator of this study, but their technique makes it easier. Surface micromachining involves the deposition and etching of different structural layers on top of the substrate, allowing the production of microstructures. Physically flexible, stretchable, and reconfigurable microstructure electronics plays an important role in fields such as 3D integrated circuits, dynamic random access memory capacitators, micromechanical systems, and metal oxide semiconductor technology. But flexible electronics require deeper etching. This, in turn, requires the use of hard masks that impose manufacturing limitations, some of which this study in Small addresses1. The scientists introduce the use of a novel hybrid mask composed of a sacrificial layer and a hard mask, which enables deep sub-millimetre etching. The sacrificial layer, which is easy-to-etch is not suitable for prolonged deep etches as it is consumed fast. However, when made of soft materials, such as polymers, the surface roughness of underlying layers is preserved and the lower layers are not contaminated. Further, the sacrificial level can be easily removed by immersion in organic solvents, such as acetone. The use of the hybrid mask allows a high aspect ratio, while preserving existing devices and structures making this approach advantageous for precise dicing, making irregular-shaped dyes, and novel packaging techniques, including Lego-like concept for pre-packaging modules and system integration. The research team is currently investigating a disruptive approach that will allow these Lego-like electronics to self-assemble. doi:10.1038/nmiddleeast.2017.34 Hussain, M. T. & Ghonein, M. M. Highly manufacturable deep (sub-millimeter) etching enabled high aspect ratio complex geometry lego-like silicon electronics. Small http://dx.doi.org/10.1002/smll.201601801 (2017).
Flexible FeRAM fabricated with CMOS-compatible approach
Nanowerk Spotlight) Making electronic devices flexible, stretchable, and even transparent has been a major research focus for quite a number of years now. By using new materials – e.g. carbon nanotubes and graphene – and designing new tools – e.g. inkjet printing – researchers have made vast strides towards flexible electronics (see for instance: "Inkjet printing of graphene for flexible electronics" or "Fully transparent, rollable electronics built with a graphene/carbon nanotube backbone"). To migrate these devices from laboratory research to large-scale industrial fabrication is still a challenge given the industry's massive investment in silicon technologies and infrastructure. Silicon-based CMOS devices still account for about 90% of today's electronics. That's why research into flexible silicon-based devices is an attractive alternative. Take for instance a recent research report that demonstrates a high performance flexible storage device based on ferroelectric material: lead zirconium titanate (PZT). In this work, reported in Advanced Electronic Materials ("Thin PZT-Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications"), researchers fabricate flexible ferroelectric random access memory (FeRAM) devices using state-of-the-art CMOS processes (sputtering, photolithography, and reactive ion etching). Posted: Jul 01, 2015 Flexible FeRAM fabricated with CMOS-compatible approach (Nanowerk Spotlight) Making electronic devices flexible, stretchable, and even transparent has been a major research focus for quite a number of years now. By using new materials – e.g. carbon nanotubes and graphene – and designing new tools – e.g. inkjet printing – researchers have made vast strides towards flexible electronics (see for instance: "Inkjet printing of graphene for flexible electronics" or "Fully transparent, rollable electronics built with a graphene/carbon nanotube backbone"). To migrate these devices from laboratory research to large-scale industrial fabrication is still a challenge given the industry's massive investment in silicon technologies and infrastructure. Silicon-based CMOS devices still account for about 90% of today's electronics. That's why research into flexible silicon-based devices is an attractive alternative. Take for instance a recent research report that demonstrates a high performance flexible storage device based on ferroelectric material: lead zirconium titanate (PZT). In this work, reported in Advanced Electronic Materials ("Thin PZT-Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications"), researchers fabricate flexible ferroelectric random access memory (FeRAM) devices using state-of-the-art CMOS processes (sputtering, photolithography, and reactive ion etching). Fabrication process flow for flexing the silicon substrate Fabrication process flow for flexing the silicon substrate. a–c) Silicon substrate with prefabricated FeRAM devices undergoes soft etch back process (upside down) to thin down the substrate to achieve d) an ultrathin version of flexible silicon with prefabricated devices. (Reprinted with permission by Wiley-VCH Verlag) "Our findings bridge the existing gap between rigid inflexible semiconductor high performance, integration density, yield, and reliable electronics and highly flexible polymer/hybrid materials based relatively low performance electronics," Muhammad Mustafa Hussain, an Associate Professor of Electrical Engineering at King Abdullah University of Science and Technology (KAUST), who led the team, tells Nanowerk. "This enables combining the best of two worlds to obtain flexible high performance electronics." "We capitalize on the existing standard CMOS fabrication processes and the well-established infrastructures to transfer the perks associated into the flexible arena through novel pragmatic microfabrication techniques to reduce the thickness of traditional silicon wafers and make today’s electronics flexible," he adds. He points out the specific results that the team specifically shows in this work: 1) record polarization, capacitance, and endurance (1 billion write-erase cycles) values reported to date for flexible ferroelectric capacitors for non-volatile memory applications; 2) uncompromised retention ability under varying dynamic stress; and 3) a minimum bending radius of 5 mm. Lead zirconium titanate (PZT) ferroelectric capacitors are already commercially used in embedded FeRAMs non-volatile memories. Hence, the technology is relatively mature. However, to obtain these PZT films a high crystallization temperature (700°C) is required to achieve the desired structural form. This temperature is way beyond the melting temperature (∼200°C) of most polymeric substrates that are inherently flexible. Therefore, researchers have been looking into alternative ferroelectric polymers to replace PZT in flexible applications. This imposes more challenges concerning the ability to integrate the devices with complementary metal-oxide-semiconductors (CMOS) based circuitries which also require high thermal budgets and require silicon for optimized high performance. "Our work utilizes the strong inverse proportionality relation between a material's thickness and its flexural modulus," explains Mohamed T. Ghoneim, a PhD student in Hussain's group and the paper's first author. "Hence, a slight decrease in thickness results in immense gains in flexibility. This enables transforming the rigid silicon substrate (∼500 µm thick) bearing the high performance monolithically integrated devices into a flexible form (40 µm thick), without detrimentally affecting the pre-fabricated devices." This concept has been confirmed in the team's work as even an intentionally non-optimized flexible form of PZT based ferroelectric capacitors on silicon surpassed the best reported values for ferroelectric capacitors built using alternative material systems. In addition, as the researchers point out, the benefits of this approach would materialize further once flexible metal-oxide-semiconductor (MOS) field effect transistors (MOSFETs) are monolithically integrated to construct memory arrays and processors at a later stage. This is because electron mobility of polymeric semiconductors is much lower than that of silicon, leading to much slower electronics in terms of operation speeds. Worth mentioning, we anticipate that polymer based flexible electronics will be suitable for niche flexible applications due to their superior inherent flexibility but where high performance is not a strict requirement," says Hussain. "We expect to see a future flexible electronics industry spanning a huge spectrum with high performance / moderate flexibility devices at one end and high flexibility / moderate performance devices at the other end." The next step for the team is to build a fully flexible PZT based FeRAM module through integrating MOS field effect access transistors with ferroelectric capacitors in a dense arraying architecture (i.e. cross bars) for a stand-alone flexible ferroelectric module and to evaluate the array performance under various out-of-plane mechanical stresses to assess the array's key memory functionalities in flexible form. By Michael Berger – Michael is author of two books by the Royal Society of Chemistry: Nano-Society: Pushing the Boundaries of Technology and Nanotechnology: The Future is Tiny. Copyright © Nanowerk
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