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This paper considers a problem of VLSI design occurring in the routing phase. The problem is to determine the optimal size selection for the gates in a combinatorial circuit which uses the problem of finding a shortest path in an oriented acyclic graph for updates between successive iterations. For this problem, an approximation algorithm is given.

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This page is a summary of: Near to Optimal Size Selection in Combinatorial Circuits, May 2012, Elsevier,
DOI: 10.3182/20120523-3-ro-2023.00060.
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