Accelerating the analysis of scheduled interference for an effective design space exploration

What is it about?

Calculating the worst-case interference of scheduled network traffic is fairly straight-forward. However, the calculation time scales with the number of time slots used in the schedule, quickly becoming impractical for design space exploration approaches, which heavily rely on formal timing analysis, where the scheduled interference has to be repeatedly calculated within a fixed-point iteration. This paper addresses this issue by proposing a preprocessing approach that significantly reduces the time needed to calculate the worst-case scheduled interference and thereby enables an efficient DSE of scheduled TSN networks.

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