Zero cost layout technique for MOSFETs
What is it about?
Describes how this innovative layout technique was invented in order to boost significantly the electrical performance and ionization radiation tolerance of MOSFETs, without add any extra costs to the CMOS ICs manufacturing processes.
Why is it important?
This layout technique can improve remarkably the electrical performance of the CMOS ICs or to reduce the die area significantly, and simultaneously to improve the ionizing radiation tolerance.
The following have contributed to this page: Dr Salvador Pinillos Gimenez