Comparison of FinFET and MOSFET adders based on various performance parameters

What is it about?

The main objective of this project is to design and implement 8-Bit low power and high speed adder structures using different logic styles in 90nm CMOS and 32nm FinFET processes. The various logic styles used for the implementation of 8-bit adders are Complementary Metal-Oxide Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG) and Gate Diffusion Input (GDI). The proposed work will aim to minimise the Dynamic Power and leakage power. The key performance metrics like dynamic power, static power, leakage power, delay, power delay product will be measured for all adder circuits implemented using various logic styles and they will be compared.

Featured Image

Photo by Alexandre Debiève on Unsplash

Photo by Alexandre Debiève on Unsplash

Why is it important?

The leakage power becomes a predominant power dissipation due to the scaling of the feature size to sub nanometer level. As the device feature size is scaled down, the threshold voltages are also scaled down to a minimum level which exponentially increases the leakage during the stand-by mode especially when all nMOS devices are in cut-off state. Hence it is mandatory to minimise the leakage power during the cut-off state of the transistors. FinFET transistors are used to minimise the leakage power since the multi-gate structure of the FinFET minimises the leakage power during cut-off state. Our results prove that, FinFET not only has exceptional performance over MOSFET but is prepped to take over MOSFET as the superior technology below 90nm.

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