What is it about?
A 1-bit full adder is designed using various logic styles and the performance of these adders are compared over a range of temperature values. 32nm FinFET Predictive Technology Model (PTM) is used for designing purpose. Various logic design styles utilised are Complementary Metal-Oxide Semiconductor (CMOS) logic, Transmission Gate (TG) logic, Complementary Pass-Transistor (CPTL) logic, Gate Diffusion Input (GDI) logic. Cadence Virtuoso and Spectre are used for designing and simulation purpose, respectively. The performance of these adders are analysed based on key circuit metrics like static power, dynamic power, leakage power, delay and power delay product (PDP).
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Why is it important?
The simulation results prove that the GDI adder structure outperforms other structures in sub nanometer technology. This advantage makes GDI technology suitable for realisation of combinational circuits.
Perspectives
Future research in digital circuits can be carried out by using GDI technology for designing low power and compact integrated circuit design.
Aalelai Vendhan
Birla Institute of Technology and Science
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This page is a summary of: Analysis on Circuit Metrics of 1-Bit FinFET Adders Realized using Distinct Logic Structures, Indian Journal of Science and Technology, July 2019, Indian Society for Education and Environment,
DOI: 10.17485/ijst/2019/v12i26/145499.
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