APP4MC: Application Platform Project for Multi- and Many-core Systems

What is it about?

Since especially the automotive domain increas- ingly utilizes multi- and many-core systems, appropriate models, analyses, and tooling are required to address chal- lenges that were nearly non existent so far. APP4MC is an open source Eclipse platform that provides AUTOSAR com- pliant common data models namely AMALTHEA, basic parallelization features, visualizations, and the great pos- sibility to add any existing tooling. For example, Eclipse Capra can be added to provide comprehensive traceabil- ity throughout the development processes but any pro- prietary, commercial, open-source, or prototypical imple- mentations can be integrated. The platform enables the creation and management of complex tool chains includ- ing performance simulation and validation. The entire community bene ts from reduced hardware costs, faster time to market, higher quality systems, and rapid adop- tion. APP4MC is not retricted to the automotive domain and utilizable in robotics or generic real-time systems as well.

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Why is it important?

With the proliferation of emission legislation and continu- ous improvement in comfort, driving and driver assistance functionalities, modern cars also continuously need more computing power. The complexity of driver assistance sys- tems in particular, are forcing designers to consider new hardware architectures such as multi- and many-core. Cur- rent development tools are not able to handle this com- plexity, pointing to a need for new, extensible tools that can be designed to meet these and future requirements. Multi-core architectures were introduced years ago in embedded systems, and it is becoming clear that there is now a need for even more powerful hardware platforms to meet future challenges. The introduction of many-core architectures has several implications for the tool chain. For instance, many-core or heterogeneous systems accom- pany an increasing number of cores to reach more com- putational power for control units. However, these archi- tectures reveal additional challenges, because the higher core amounts require the chip to house more complex net- work architectures. Compared to multi-core systems the underlying architecture (network-on-chip) di ers in sev- eral ways. Description capabilities of existing hardware as well as software models need to be extended. Further- more, by introducing extended models, new tools and techniques are required to make e ective use of the result- ing level of parallelism, as well as for optimizing the per- formance of the new architecture.

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