Defect-tolerance routing for wafer-scale chip

What is it about?

Wafer-scale chips put nearly a million processors on one silicon wafer, but each wafer typically has a few dozen manufacturing defects. Today’s chips switch off whole rows and columns containing them, losing tens of thousands of working processors. Earlier fault-tolerant routing methods route around the defects instead, but most need far more memory than each processor has. DLR splits the nearly intact chip into defect-free rectangles, keeping every working processor in use with only about 100 bytes of routing information each.

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Photo by Igor Shalyminov on Unsplash

Photo by Igor Shalyminov on Unsplash

Why is it important?

A wafer-scale chip integrates a huge amount of SRAM and computing power on monolithic silicon. Keeping data on-chip gives it enormous bandwidth, making it a promising platform for AI models. But unlike ordinary chips, which can simply be discarded when defective, defects must be tolerated on wafer-scale-chip. DLR does this without switching off healthy processors, reclaiming the tens of thousands that today’s chips lose, wherever the defects fall.