PANDA: A Dataflow Chip with Adaptive Prefetching and Decentralized Scheduling

What is it about?

We propose PANDA, a novel dataflow architecture that improves performance through adaptive prefetching and decentralized scheduling. Rather than relying on rigid memory access and centralized control, PANDA introduces an application-adaptive prefetching method with a reconfigurable on-chip memory architecture, as well as a distributed dynamic scheduling strategy built on decentralized processing elements (PEs). Through hardware-software co-optimization of the dataflow execution model, PANDA effectively reduces memory access latency and improves hardware utilization. Evaluated on a wide range of real-world applications, PANDA achieves up to 2.53× performance improvement and 1.79× energy-efficiency improvement over state-of-the-art dataflow architectures.

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Photo by A Chosen Soul on Unsplash

Photo by A Chosen Soul on Unsplash

Why is it important?

Dataflow architectures offer an attractive balance of performance, energy efficiency, and flexibility, making them a strong candidate for future computing systems. However, their practical performance is often limited by two key bottlenecks: inefficient memory access and centralized task scheduling. Existing designs struggle to efficiently support both regular and irregular memory access patterns, while centralized control can introduce communication overhead and reduce hardware utilization. PANDA addresses these challenges through adaptive prefetching, a reconfigurable on-chip memory architecture, and decentralized dynamic scheduling. By reducing memory access latency and improving processing element utilization, PANDA provides a practical way to make dataflow architectures faster and more efficient for real-world applications.

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