What is it about?
The SHARC simulator uses simulations of a control system's physics and the execution of its controller on a given CPU to generate accurate trajectories that incorporate the computational delays required to execute the controller. The CPU simulator executes simulations of compiled controller binaries---the same binaries as would be deployed on hardware---to determine the number of CPU cycles required to run the control algorithm.
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Why is it important?
Many theoretical results guarantee the performance of cyber-physical systems under the assumption that delays are negligible. Deployment on real systems always introduces computational delays which can ruin the theoretical guarantees. The SHARC simulator allows researchers and engineers to jointly test and optimize their controller and computational hardware to ensure that the system performs well.
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This page is a summary of: Sharc: Simulator for Hardware Architecture and Real-time Control, May 2025, ACM (Association for Computing Machinery),
DOI: 10.1145/3716863.3718046.
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