What is it about?
This work aims to enhance the capabilities of existing software tools for timing analysis by integrating Machine Learning-based Neural Twins to accurately account for various process variations and aging effects in integrated circuits. Our framework, ML-TIME, improves traditional static timing analysis, allowing us to identify circuits vulnerable to delays caused by process variations and aging, thus improving circuit reliability and design optimization. Our framework demonstrates high accuracy across multiple benchmarks. It is easy to integrate into existing software tools and timing analysis workflows. Additionally, it shows significant speed-up compared to state-of-the-art software tools that rely on computationally expensive simulations and is easy to fine-tune to different technology nodes or user-specific manufacturing variations.
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Why is it important?
As technology advances and chips become ever more complex, factors such as process variation and aging increasingly affect the reliability and performance of integrated circuits. However, state-of-the-art software tools for static timing analysis do not account for process variations, aging, or a combination of both. Therefore, our framework ML-TIME improves circuit robustness, reduces early life failures, and allows better and more efficient design optimization under real-world variations in manufacturing processes.
Perspectives
Our framework, ML-TIME, helps to address the limitations of traditional static timing analysis tools by incorporating process variations and aging effects that are significant reliability challenges, leading to increased path delays and early-life failures. Using Machine Learning-based Neural Twins enables us to predict statistical distributions over path delays instead of only analyzing corner cases. Thus, our framework has the potential to improve design robustness and identify critical paths affected by process variations and aging, resulting in more reliable circuit designs.
Peter Domanski
University of Stuttgart
Read the Original
This page is a summary of: ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging Effects, September 2024, ACM (Association for Computing Machinery),
DOI: 10.1145/3670474.3685968.
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