What is it about?
Memristor enables logic operations within the memory array, where memristors in the same row or column serve as a logic gate. Logic functions are implemented in the memory through netlist synthesis and in-memory mapping, which assigns each gate operation to specific memristors. The goal is to minimize latency, which represents the number of clock cycles required to complete the operations. We propose two approaches: (1) graph coloring-based in-memory mapping, and (2) integration with mapping-aware netlist synthesis.
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Why is it important?
While multiple gate operations can be executed in the same clock cycle, additional cycles may be needed for copy operations to align the gate operations. Therefore, assigning each operation to a clock cycle is a challenge. Furthermore, the results of in-memory mapping vary depending on the input netlist. To further reduce latency, an integrated approach is necessary to provide an optimal netlist.
Perspectives
While writing this paper, I hope that my ideas would bring significant innovation to the semiconductor industry. I aim for this paper to present a new paradigm of transitioning from the current CPU-centric architecture to a PIM-centric architecture. By doing so, I aspire to contribute to the advancement of the semiconductor industry and provide an efficient computing environment, achieving both performance improvements and energy savings across various applications.
Seunggyu Lee
KAIST
Read the Original
This page is a summary of: Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic, June 2024, ACM (Association for Computing Machinery),
DOI: 10.1145/3649476.3658758.
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