Agile Hardware Design

What is it about?

With the recent increase in the complexity of image processing and machine learning algorithms, there has been significant growth in the development of hardware accelerators for these applications. In the chip design process, hardware engineers study an application and then generate hardware they think will efficiently accelerate that application. Then, a group of software engineers develop a compiler to map applications onto the proposed accelerator system. This “waterfall approach” leads to long design times. Our work uses new programming languages for specifying the hardware and formal techniques to generate the compiler collateral alongside the hardware, making the chip design process much more agile. The engineer designs the accelerator for an application using our Python-based design languages and the compiler is automatically generated, giving the engineer instant feedback on the application performance and efficiency. This reduces the time it takes to design chips and allows for much more design exploration.

Featured Image

Photo by Brian Kostiuk on Unsplash

Photo by Brian Kostiuk on Unsplash

Why is it important?

It is well known that the driving force behind increasing chip performance and energy efficiency in the last several decades, Moore’s law, is slowing down significantly. At the same time, applications for machine learning and artificial intelligence are rapidly increasing in complexity and variety. This combination of factors has led to the increased interest in designing accelerators that achieve high performance and energy efficiency. Our work creates a methodology for fast accelerator development and gives the designer fast feedback on the quality of their design. In addition, our paper describes a coarse grained accelerator we designed using our methodology that can accelerate a variety of image processing and machine learning applications and demonstrates competitive performance and better energy efficiency versus modern CPUs and GPUs.