Chip PPA optimization utilizing multi-bit flip-flop cells

What is it about?

Using multi-bit flip-flop(MBFF) cells in the chip implementation effectively reduces power consumption, especially on the flip-flops and the clock network. We solved two new challenges of MBFF in physical design and proposed DTCO flow utilizing MBFF cells to improve chip PPA.

Featured Image

Photo by Adi Goldstein on Unsplash

Photo by Adi Goldstein on Unsplash

Why is it important?

We overcome the less flexible cell flipping problem and the space waste problem in MBFF cell footprint by designing D-to-Q flow flipping MBFF cell and transistor upsized MBFF cell. These are integrated into our proposed DTCO framework in the placement and routing stages. Our experiments showed that our proposed DTCO flow optimizing MBFF cells produces chip implementations with 24.6% fewer design rule violations and 14.9% reduced worst timing slack with a little power fluctuation than that produced by the conventional design flow with MBFFs.